Methods and devices for forming nanostructure monolayers and devices including such monolayers

ABSTRACT

Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing also are provided.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. patent application Ser. No. 13/098,082 filed Apr. 29, 2011, now U.S. Pat. No. ______, which is a division of U.S. patent application Ser. No. 11/881,739, filed Jul. 27, 2007, now U.S. Pat. No. 7,968,273, which is a continuation-in-part of U.S. patent application Ser. No. 11/495,188, filed Jul. 28, 2006, now U.S. Pat. No. 7,776,758, which is a continuation-in-part of U.S. patent application Ser. No. 11/148,001, filed Jun. 7, 2005, now U.S. Pat. No. 7,501,315, which claims priority to and benefit of the following prior provisional patent applications: U.S. Provisional Patent Application Ser. No. 60/671,134, filed Apr. 13, 2005, U.S. Provisional Patent Application Ser. No. 60/632,570, filed Nov. 30, 2004, and U.S. Provisional Patent Application Ser. No. 60/578,236, filed Jun. 8, 2004, each of which is incorporated herein by reference in its entirety for all purposes.

BACKGROUND

This invention relates primarily to the field of nanotechnology. More specifically, the invention pertains to methods and devices for forming nanostructure arrays, e.g., monolayer arrays, e.g., of predetermined size and/or at predetermined positions, and to devices (e.g., memory devices) including such nanostructure arrays. The invention also relates to methods for protecting nanostructures from fusion during high temperature processing.

Monolayers of nanostructures (e.g., quantum dots) can serve as components of a variety of optoelectronic devices such as LEDs and memory devices (see, e.g., Flagan et al. U.S. Pat. No. 6,586,785). Methods for producing such monolayers include growing quantum dots in situ on a solid by molecular beam epitaxy, and exploiting phase segregation between aliphatic surfactants on quantum dots and aromatic conjugated organic materials deposited on the dots (Coe et al. “Electroluminescence from single monolayers of nanocrystals in molecular organic devices” Nature 450:800-803 (2002)). However, the former technique is difficult to scale up to form large numbers of monolayers, and the latter technique produces a layer of nanostructures embedded in or disposed on a thick organic matrix whose presence is undesirable in many device fabrication processes.

Methods for simply and reproducibly forming nanostructure monolayers are thus desirable. Among other aspects, the present invention provides such methods. A complete understanding of the invention will be obtained upon review of the following.

SUMMARY

Methods for patterning nanostructure arrays, e.g., ordered or disordered monolayer arrays, and for protecting nanostructures from fusion during high temperature processing are described. Devices including nanostructure arrays are also provided.

One general class of embodiments provides methods for patterning a nanostructure monolayer. The methods include a) disposing resist and a monolayer of nanostructures on a first layer, wherein the nanostructures are embedded in the resist, to provide a resist layer, b) exposing a predetermined pattern on the resist layer (e.g., to ionizing radiation such as ultraviolet light or an electron beam), to provide exposed resist in at least a first region of the resist layer and unexposed resist in at least a second region of the resist layer, c) removing the unexposed resist and its embedded nanostructures from the first layer without removing the exposed resist and its embedded nanostructures, whereby at least one nanostructure monolayer array defined by the first region remains on the first layer, and d) after step c), exposing the first layer, the exposed resist and its embedded nanostructures to a temperature of at least about 300° C. (e.g., at least about 700° C. or at least about 900° C.).

In one particularly useful aspect, the resist is incompletely cured by initial low dose or brief exposure to pattern the monolayer, unexposed resist and undesired nanostructures embedded therein are removed, and the incompletely cured resist is then further cured with a second exposure to protect the nanostructures from subsequent high temperature step(s). Thus, in one class of embodiments, in step b) the resist in the first region is exposed to ionizing radiation sufficient to incompletely cure the resist in the first region, and then, after step c) and before step d), the incompletely cured resist in the first region is exposed to ionizing radiation sufficient to further cure the resist in the first region. As one example, in step b) the resist in the first region can be exposed to about 10 mJ/cm²-1 J/cm² ultraviolet light to incompletely cure the resist in the first region, and, after step c) and before step d), the resist in the first region can be exposed to about 1 J/cm²-50 J/cm² ultraviolet light to further cure the resist in the first region.

The methods can protect the nanostructures from fusion at elevated temperatures, thus maintaining nanostructure density, size, size distribution, monolayer morphology, etc., during high temperature processing steps. Accordingly, in one class of embodiments, the density of nanostructures in the monolayer array after step d) is at least 75% of the density of nanostructures in the monolayer array before step d), more typically, at least 90% or at least 95%. Optionally, the density is essentially unchanged during step d). Optionally, following step d), the monolayer array of nanostructures has a density greater than about 1×10¹⁰ nanostructures/cm², e.g., greater than about 1×10¹¹ nanostructures/cm², greater than about 1×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², at least 5×10¹² nanostructures/cm², or even at least about 1×10¹³ nanostructures/cm². Optionally, density of the nanostructures in the monolayer array is substantially uniform following step d).

In a related class of embodiments, the average diameter of the nanostructures in the monolayer array after step d) is less than 110% of the average diameter of the nanostructures in the monolayer array before step d), for example, less than 105% or less than 103%. Optionally, the size distribution of the nanostructures in the array is essentially unchanged during step d).

In another related class of embodiments, following step d), the size distribution of the nanostructures in the monolayer array exhibits an rms deviation of less than 20%. For example, the size distribution of the nanostructures in the monolayer array can exhibit an rms deviation of less than 15%, less than 10%, or even less than 5%.

It will be evident that the tendency of nanostructures to fuse is greater at higher initial nanostructure densities, and thus protection from fusion is increasingly important with increasing nanostructure density. Thus, in embodiments in which, e.g., preservation of nanostructure density, monolayer uniformity, nanostructure size, and/or nanostructure size distribution is of interest, the density of nanostructures in the monolayer array before step d) is optionally at least about 1×10¹⁰ nanostructures/cm², e.g., at least about 1×10¹¹ nanostructures/cm², at least about 1×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², at least 5×10¹² nanostructures/cm², or even at least about 1×10¹³ nanostructures/cm².

The resist layer can be formed in step a) by essentially any convenient technique. For example, the first layer can be spin coated with a solution comprising the resist and the nanostructures. Similarly, unexposed resist can be removed in step c) by essentially any convenient technique. For example, the unexposed resist and its embedded nanostructures can be removed from the first layer without removing the exposed resist and its embedded nanostructures by contacting the unexposed resist with at least one organic solvent.

In one class of embodiments, the resist comprises a silicon compound. For example, the resist can be a silsesquioxane, such as mercapto-propyl-cyclohexyl polyhedral oligomeric silsesquioxane, hydrogen silsesquioxane, methyl silsesquioxane, octavinyl dimethyl silyl silsesquioxane, octasilane silsesquioxane, octavinyl-T8 silsesquioxane, aminopropylcyclohexyl polyhedral oligomeric silsesquioxane, acrylo silsesquioxane, or methacrylo silsesquioxane.

The methods can be used to produce essentially any number of monolayer arrays. For example, exposed resist can be provided in two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more discrete first regions of the resist layer, such that a like number of discrete nanostructure monolayer arrays remains on the first layer.

The first layer can comprise essentially any desired material, including, but not limited to, a semiconductor or a dielectric material such as an oxide (e.g., a metal oxide, silicon oxide, hafnium oxide, or alumina (Al₂O₃), or a combination of such oxides) or a nitride (e.g., silicon nitride). The first layer is optionally treated prior to disposition of the solution, e.g., with a compound such as hexamethyldisilizane (HMDS) or a silane. Thus, for example, the first layer can comprise silicon oxide or silicon nitride coated with HMDS. The first layer is optionally disposed on a substrate, e.g., a substrate comprising a semiconductor (e.g., Si). In one class of embodiments, the first layer has a thickness of between about 1 nm and about 10 nm, e.g., between 3 and 4 nm. The methods optionally include forming a source region and a drain region in the substrate in proximity to the monolayer array of nanostructures by, prior to step d), implanting dopant ions in the substrate, wherein implantation damage to the substrate is repaired and the dopant is activated during step d). A gate electrode can be disposed on the exposed resist, optionally after a dielectric layer is disposed on the exposed resist.

The array can be an ordered or disordered array. The nanostructures are optionally substantially spherical nanostructures or quantum dots. The nanostructures can comprise essentially any desired material. In one class of embodiments, the nanostructures have a work function of about 4.5 eV or higher. For example, the nanostructures can comprise a metal, e.g., palladium, platinum, nickel, or ruthenium. In some embodiments, a second monolayer of nanostructures is disposed on the resist layer or on the exposed resist.

Another general class of embodiments provides methods for protecting nanostructures from fusion during high temperature processing. The methods include a) disposing the nanostructures and a silsesquioxane on a first layer, b) curing the silsesquioxane, to provide cured silsesquioxane in which the nanostructures are embedded, and c) heating the first layer, the cured silsesquioxane, and its embedded nanostructures.

The nanostructures and the silsesquioxane can be disposed on the first layer using essentially any convenient technique. For example, the first layer can be spin coated with a solution comprising the silsesquioxane and the nanostructures. The nanostructures can, but need not, form a monolayer on the first layer.

The silsesquioxane can be cured by heating, for example, by exposure to a temperature between about 300° C. and 400° C. As another example, the silsesquioxane can be cured by exposure to ionizing radiation, e.g., sufficient to essentially completely cure the silsesquioxane. In a particularly useful aspect, the silsesquioxane is incompletely cured as the nanostructures are patterned and is then subsequently further cured.

Thus, in one class of embodiments, in step b) curing the silsesquioxane comprises b) i) exposing the silsesquioxane to ionizing radiation in a predetermined pattern, whereby the silsesquioxane in at least a first region is exposed and incompletely cured while the silsesquioxane in a least a second region remains unexposed and uncured, b) ii) removing the unexposed silsesquioxane and nanostructures therein from the second region without removing the incompletely cured silsesquioxane and its embedded nanostructures from the first region, and b) iii) after step ii), exposing the incompletely cured silsesquioxane in the first region to ionizing radiation to further cure the silsesquioxane, to provide the cured silsesquioxane. In one exemplary class of embodiments, in step b) i) the silsesquioxane in the first region is exposed to about 10 mJ/cm²-1 J/cm² ultraviolet light to incompletely cure the silsesquioxane in the first region, and in step b) iii) the incompletely cured silsesquioxane in the first region is exposed to about 1 J/cm²-50 J/cm² ultraviolet light to further cure the silsesquioxane in the first region. Unexposed silsesquioxane and nanostructures therein can be removed from the second region without removing the incompletely cured silsesquioxane and its embedded nanostructures from the first region by, e.g., contacting the unexposed silsesquioxane with at least one organic solvent. After step b) iii) and before step c), the cured silsesquioxane is optionally exposed to a temperature between about 300° C. and 400° C.

Optionally, in step c) the first layer, the cured silsesquioxane, and its embedded nanostructures are exposed to a temperature of at least about 300° C. (typically, following step b), typically at least about 700° C. or at least about 900° C. For example, the first layer, the cured silsesquioxane, and its embedded nanostructures can be exposed to a temperature of 950° C. or more, for example, during a high-temperature annealing step.

As noted above, the nanostructures disposed on the first layer optionally comprise a monolayer. In embodiments in which a monolayer is patterned in step b), in step b) ii) at least one nanostructure monolayer array defined by the first region remains on the first layer.

As described above, by protecting the nanostructures from fusion, the methods can maintain nanostructure density, size, size distribution, monolayer morphology, etc., during high temperature processing steps. For example, in one class of embodiments in which the nanostructures were disposed in a monolayer, the density of nanostructures in the monolayer array after step c) is at least 90% of the density of nanostructures in the monolayer array before step c). As described above, protection from fusion is increasingly important with increasing nanostructure density. Thus, the density of nanostructures in the monolayer array before step c) is optionally at least about 1×10¹° nanostructures/cm², e.g., at least about 1×10¹¹ nanostructures/cm², at least about 1×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², or at least 5×10¹² nanostructures/cm². In one class of embodiments, following step c), the monolayer array of nanostructures has a density greater than about 1×10¹² nanostructures/cm², e.g., at least 2.5×10¹² nanostructures/cm² or at least 5×10¹² nanostructures/cm². Optionally, density of the nanostructures in the monolayer array is substantially uniform following step c).

In one class of embodiments, the average diameter of the nanostructures embedded in the cured silsesquioxane after step c) is less than 110% of the average diameter of the nanostructures embedded in the cured silsesquioxane before step c). In a related class of embodiments, the size distribution of the nanostructures embedded in the cured silsesquioxane exhibits an rms deviation of less than 20%. For example, following step c), the size distribution of the nanostructures embedded in the cured silsesquioxane can exhibit an rms deviation of less than 15%, less than 10%, or even less than 5%.

In embodiments in which the nanostructures are disposed in a monolayer, the methods optionally include disposing one or more additional monolayers on the monolayer. For example, in one class of embodiments, the methods include, after step b) i) and prior to step b) iii), disposing a second monolayer of nanostructures in silsesquioxane on the incompletely cured silsesquioxane.

Essentially all of the features noted for the embodiments above apply to these embodiments as well, as relevant; for example, with respect to composition of the first layer, disposition of the first layer on a substrate, composition of the substrate, nanostructure shape and composition, type of silsesquioxane, and the like. For example, the nanostructures are optionally substantially spherical nanostructures or quantum dots. In one class of embodiments, the nanostructures have a work function of about 4.5 eV or higher. For example, the nanostructures can comprise a metal, e.g., palladium, platinum, nickel, or ruthenium.

Also as for the embodiments above, in embodiments in which one or more monolayer arrays are patterned, the methods optionally include incorporation of the array(s) into transistor(s). Thus, for example, the methods optionally include forming a source region and a drain region in the substrate in proximity to the monolayer array of nanostructures by, prior to step c), implanting dopant ions in the substrate, wherein implantation damage to the substrate is repaired and the dopant is activated during step c). A gate electrode can be disposed on the cured silsesquioxane, optionally after a dielectric layer is disposed on the cured silsesquioxane.

Another general class of embodiments provides a device that includes a substrate and two or more nanostructure arrays disposed on the substrate. The substrate comprises a semiconductor, and each nanostructure array comprises a monolayer and is disposed at a predetermined position on the substrate. For each monolayer array, the substrate comprises an activated source region, an activated drain region, and a channel region between the source and drain regions and underlying the monolayer array of nanostructures.

Suitable substrates include, but are not limited to, a quartz substrate or a silicon wafer or a portion thereof. A first layer is optionally disposed between the monolayer arrays and the substrate. In one class of embodiments, the first layer comprises a dielectric material and has a thickness of between about 1 nm and about 10 nm, e.g., between 3 and 4 nm. In some embodiments, a control dielectric layer is disposed on each monolayer array of nanostructures, and a gate electrode is disposed on each control dielectric layer.

Essentially all of the features noted for the embodiments above apply to these embodiments as well, as relevant; for example, with respect to nanostructure shape and composition, inclusion of preformed nanostructures, and the like. For example, the nanostructures are optionally substantially spherical nanostructures or quantum dots. In one class of embodiments, the nanostructures have a work function of about 4.5 eV or higher. For example, the nanostructures can comprise a metal, e.g., palladium, platinum, nickel, or ruthenium. The nanostructure arrays are optionally embedded in a cured (partially or essentially completely cured) resist, a cured silsesquioxane, silicon dioxide, or the like.

The device is optionally produced by a method of the invention, and thus, as described above, can include nanostructures with a narrow size distribution. Accordingly, in one class of embodiments, the size distribution of the nanostructures in the monolayer arrays exhibits an rms deviation of less than 20%, for example, less than 15%, less than 10%, or even less than 5%.

In one class of embodiments, the arrays have a high density of nanostructures. For example, each nanostructure array optionally has a density greater than about 1×10¹⁰ nanostructures/cm², greater than about 1×10¹¹ nanostructures/cm², greater than about 1×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², at least 5×10¹² nanostructures/cm², or even greater than about 1×10¹³ nanostructures/cm². Optionally, as described above, density of the nanostructures in each monolayer array is substantially uniform.

In one class of embodiments, each of the two or more monolayer arrays of nanostructures disposed on the substrate has an additional monolayer array (or two or more additional arrays) of nanostructures disposed thereon. A dielectric layer is optionally disposed between adjacent monolayers.

Yet another general class of embodiments provides a memory device that includes at least one transistor, which transistor comprises a gate area that is occupied by a monolayer array of nanostructures, an activated source region, and an activated drain region. The size distribution of the nanostructures in the monolayer array exhibits an rms deviation of less than 20%. For example, the size distribution of the nanostructures in the monolayer array can exhibit an rms deviation of less than 15%, less than 10%, or even less than 5%. Optionally, density of the nanostructures in the monolayer array is substantially uniform. The at least one transistor can comprise two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, or 1×10¹² or more transistors.

Essentially all of the features noted for the embodiments above apply to these embodiments as well, as relevant; for example, with respect to nanostructure shape and composition, inclusion of preformed nanostructures, inclusion of a second monolayer array on the first, and the like. The monolayer array optionally has a density greater than about 1×10¹⁰ nanostructures/cm², greater than about 1×10¹¹ nanostructures/cm², greater than about 1×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², at least 5×10¹² nanostructures/cm², or greater than about 1×10¹³ nanostructures/cm². The nanostructures in the array are optionally embedded in a cured resist, a cured silsesquioxane, silicon dioxide, or the like, as described above.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 Panels A-C schematically illustrate formation of monolayer arrays of nanostructures on a coated first layer, where discrete regions of the first layer are coated.

FIG. 2 Panels A-D schematically illustrate formation of monolayer arrays of nanostructures on a coated first layer, where the coating composition is photoactivatable and discrete regions of the first layer are exposed to light to initiate cross-linking of the composition to ligands on the nanostructures.

FIG. 3 Panel A depicts an exemplary monothiol silsesquioxane ligand, while Panel B depicts an exemplary trithiol silsesquioxane ligand. Panel C depicts an exemplary amine POSS ligand. In Panels A-C, R can be an organic group or a hydrogen atom; for example, R can be a hydrocarbon group, an alkyl group (e.g., a cyclic alkyl group or a short alkyl group having fewer than 20 or even fewer than 10 carbon atoms), an aryl group, an alkylaryl group, an alkenyl group, or an alkynyl group. For example, in some embodiments, R is an isobutyl group, a methyl group, a hexyl group, or a cyclopentyl group. In certain embodiments, R is a cyclohexyl group. Panel D depicts a methacrylo silsesquioxane. Panel E depicts an acrylo silsesquioxane.

FIG. 4 schematically illustrates fabrication of a flash transistor comprising a monolayer array of nanostructures, including use of resist to pattern the monolayer.

FIG. 5 Panels A-D schematically illustrate formation of a monolayer array of nanostructures using a device of the invention. A side view of the device is schematically depicted in Panels A-C.

FIG. 6 Panels A-B schematically illustrate fabrication of devices for forming nanostructure arrays. Side views of the devices are shown.

FIG. 7 Panels A-C schematically illustrate exemplary devices of the invention. Panel A depicts a top view of a device. Panel B presents a cross section of the device shown in Panel A, and outlines formation of a monolayer array of nanostructures using the device. Panel C depicts a cross section of another exemplary device.

FIG. 8 presents micrographs of palladium (Panel A), ruthenium (Panel B), and nickel (Panel C) quantum dots formed by deposition of the dots in a spin-on-glass.

FIG. 9 presents micrographs of quantum dots before (Panel A) and after (Panel B) solvent annealing to improve monolayer quality.

FIG. 10 schematically illustrates patterning of a monolayer array of nanostructures embedded in resist.

FIG. 11 presents micrographs of quantum dots patterned using methods of the invention.

FIG. 12 Panels A-C present micrographs of ruthenium quantum dots in silsesquioxane after exposure to 950° C., where the dots were not protected by previous curing of the silsesquioxane (Panel A) or were protected by previous UV curing of the silsesquioxane for 15 minutes (Panel B) or 100 minutes (Panel C).

FIG. 13 schematically illustrates fabrication of a flash transistor comprising a monolayer array of nanostructures, including use of resist to pattern and protect the monolayer.

Figures are not necessarily to scale.

DEFINITIONS

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention pertains. The following definitions supplement those in the art and are directed to the current application and are not to be imputed to any related or unrelated case, e.g., to any commonly owned patent or application. Although any methods and materials similar or equivalent to those described herein can be used in the practice for testing of the present invention, the preferred materials and methods are described herein. Accordingly, the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.

As used in this specification and the appended claims, the singular forms “a,” “an” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a nanostructure” includes a plurality of such nanostructures, and the like.

The term “about” as used herein indicates the value of a given quantity varies by +/−10% of the value, or optionally +/−5% of the value, or in some embodiments, by +/−1% of the value so described.

A “nanostructure” is a structure having at least one region or characteristic dimension with a dimension of less than about 500 nm, e.g., less than about 200 nm, less than about 100 nm, less than about 50 nm, or even less than about 20 nm. Typically, the region or characteristic dimension will be along the smallest axis of the structure. Examples of such structures include nanowires, nanorods, nanotubes, branched nanostructures, nanotetrapods, tripods, bipods, nanocrystals, nanodots, quantum dots, nanoparticles, and the like. Nanostructures can be, e.g., substantially crystalline, substantially monocrystalline, polycrystalline, amorphous, or a combination thereof. In one aspect, each of the three dimensions of the nanostructure has a dimension of less than about 500 nm, e.g., less than about 200 nm, less than about 100 nm, less than about 50 nm, or even less than about 20 nm.

An “aspect ratio” is the length of a first axis of a nanostructure divided by the average of the lengths of the second and third axes of the nanostructure, where the second and third axes are the two axes whose lengths are most nearly equal each other. For example, the aspect ratio for a perfect rod would be the length of its long axis divided by the diameter of a cross-section perpendicular to (normal to) the long axis.

As used herein, the “diameter” of a nanostructure refers to the diameter of a cross-section normal to a first axis of the nanostructure, where the first axis has the greatest difference in length with respect to the second and third axes (the second and third axes are the two axes whose lengths most nearly equal each other). The first axis is not necessarily the longest axis of the nanostructure; e.g., for a disk-shaped nanostructure, the cross-section would be a substantially circular cross-section normal to the short longitudinal axis of the disk. Where the cross-section is not circular, the diameter is the average of the major and minor axes of that cross-section. For an elongated or high aspect ratio nanostructure, such as a nanowire or nanorod, a diameter is typically measured across a cross-section perpendicular to the longest axis of the nanowire or nanorod. For spherical nanostructures such as quantum dots, the diameter is measured from one side to the other through the center of the sphere.

The terms “crystalline” or “substantially crystalline,” when used with respect to nanostructures, refer to the fact that the nanostructures typically exhibit long-range ordering across one or more dimensions of the structure. It will be understood by one of skill in the art that the term “long range ordering” will depend on the absolute size of the specific nanostructures, as ordering for a single crystal cannot extend beyond the boundaries of the crystal. In this case, “long-range ordering” will mean substantial order across at least the majority of the dimension of the nanostructure. In some instances, a nanostructure can bear an oxide or other coating, or can be comprised of a core and at least one shell. In such instances it will be appreciated that the oxide, shell(s), or other coating need not exhibit such ordering (e.g., it can be amorphous, polycrystalline, or otherwise). In such instances, the phrase “crystalline,” “substantially crystalline,” “substantially monocrystalline,” or “monocrystalline” refers to the central core of the nanostructure (excluding the coating layers or shells). The terms “crystalline” or “substantially crystalline” as used herein are intended to also encompass structures comprising various defects, stacking faults, atomic substitutions, and the like, as long as the structure exhibits substantial long range ordering (e.g., order over at least about 80% of the length of at least one axis of the nanostructure or its core). In addition, it will be appreciated that the interface between a core and the outside of a nanostructure or between a core and an adjacent shell or between a shell and a second adjacent shell may contain non-crystalline regions and may even be amorphous. This does not prevent the nanostructure from being crystalline or substantially crystalline as defined herein.

The term “monocrystalline” when used with respect to a nanostructure indicates that the nanostructure is substantially crystalline and comprises substantially a single crystal. When used with respect to a nanostructure heterostructure comprising a core and one or more shells, “monocrystalline” indicates that the core is substantially crystalline and comprises substantially a single crystal.

A “nanocrystal” is a nanostructure that is substantially monocrystalline. A nanocrystal thus has at least one region or characteristic dimension with a dimension of less than about 500 nm, e.g., less than about 200 nm, less than about 100 nm, less than about 50 nm, or even less than about 20 nm. The term “nanocrystal” is intended to encompass substantially monocrystalline nanostructures comprising various defects, stacking faults, atomic substitutions, and the like, as well as substantially monocrystalline nanostructures without such defects, faults, or substitutions. In the case of nanocrystal heterostructures comprising a core and one or more shells, the core of the nanocrystal is typically substantially monocrystalline, but the shell(s) need not be. In one aspect, each of the three dimensions of the nanocrystal has a dimension of less than about 500 nm, e.g., less than about 200 nm, less than about 100 nm, less than about 50 nm, or even less than about 20 nm. Examples of nanocrystals include, but are not limited to, substantially spherical nanocrystals, branched nanocrystals, and substantially monocrystalline nanowires, nanorods, nanodots, quantum dots, nanotetrapods, tripods, bipods, and branched tetrapods (e.g., inorganic dendrimers).

A “substantially spherical nanostructure” is a nanostructure with an aspect ratio between about 0.8 and about 1.2. For example, a “substantially spherical nanocrystal” is a nanocrystal with an aspect ratio between about 0.8 and about 1.2.

A “nanostructure array” is an assemblage of nanostructures. The assemblage can be spatially ordered (an “ordered array”) or disordered (a “disordered array”). In a “monolayer array” of nanostructures, the assemblage of nanostructures comprises a monolayer.

A variety of additional terms are defined or otherwise characterized herein.

DETAILED DESCRIPTION

In one aspect, the invention provides methods for forming nanostructure arrays, e.g., ordered or disordered monolayer arrays of nanostructures. The arrays are optionally formed at predetermined positions and/or have predetermined dimensions. Devices related to the methods are also provided, as are devices including nanostructure arrays. For example, in one aspect, the invention provides memory devices including small monolayer arrays of nanostructures.

Monolayer Formation on Chemical Coatings

A surface on which a nanostructure array is to be formed can be coated with a chemical composition, e.g., a composition having a higher affinity for the nanostructures than the surface itself does. Such a coating can, e.g., facilitate adhesion of the nanostructures to the surface and can thus facilitate formation of the monolayer.

Thus, one general class of embodiments provides methods for forming a nanostructure array. In the methods, a first layer is provided and coated with a composition comprising a nanostructure association group, to provide a coated first layer. A population of nanostructures is deposited on the coated first layer, whereby the nanostructures associate with the nanostructure association group. Any nanostructures which are not associated with the nanostructure association group are removed, whereby a monolayer array of nanostructures remains associated with the coated first layer.

The first layer can comprise essentially any desired material, chosen, e.g., based on the use to which the resulting monolayer array of nanostructures is to be put (e.g., a conductive material, a nonconductive material, a semiconductor, or the like). The first layer is optionally disposed or deposited on a substrate, which can similarly comprise essentially any desired material, depending, e.g., on the desired use of the nanostructure array. Suitable substrates include, but are not limited to: a uniform substrate, e.g., a wafer of solid material, such as silicon or other semiconductor material, glass, quartz, polymerics, etc.; a large rigid sheet of solid material, e.g., glass, quartz, plastics such as polycarbonate, polystyrene, etc.; a flexible substrate, such as a roll of plastic such as polyolefin, polyamide, and others; or a transparent substrate. Combinations of these features can be employed. The substrate optionally includes other compositional or structural elements that are part of an ultimately desired device. Particular examples of such elements include electrical circuit elements such as electrical contacts, other wires or conductive paths, including nanowires or other nanoscale conducting elements, optical and/or optoelectrical elements (e.g., lasers, LEDs, etc.), and structural elements (e.g., microcantilevers, pits, wells, posts, etc.).

For example, in embodiments in which the monolayer array of nanostructures is to be incorporated into a flash transistor or memory device, the first layer comprises a dielectric material, such as an oxide (e.g., a metal oxide, silicon oxide, hafnium oxide, or alumina (Al₂O₃), or a combination of such oxides), a nitride (e.g., Si₃N₄), an insulating polymer, or another nonconductive material. In this class of embodiments, the first layer (which serves as a tunnel dielectric layer in these embodiments) is preferably thin (e.g., has a thickness of between about 1 nm and about 10 nm, e.g., between 3 and 4 nm), and is disposed on a substrate that comprises a semiconductor. Preferred tunnel dielectrics are described in Chen U.S. Patent Publication No. 2008/0150009, which is herein incorporated by reference in its entirety. The substrate typically includes a source region, a drain region, and a channel region between the source and drain regions and underlying the monolayer array of nanostructures, and the methods include disposing a control dielectric layer on the monolayer array of nanostructures and disposing a gate electrode on the control dielectric layer, thus incorporating the nanostructure array into a transistor. The control dielectric layer comprises a dielectric material, for example, an oxide (e.g., a metal oxide, SiO₂, or Al₂O₃, or a combination of such oxides), an insulating polymer, or another nonconductive material. Preferred control dielectrics are described in Chen U.S. Patent Publication No. 2008/0150009 (supra), and preferred gate electrode design is described in Duan et al. U.S. Pat. No. 8,030,161, each of which is herein incorporated by reference in its entirety.

The methods can be used to form multiple nanostructure arrays on the same surface. Thus, in one class of embodiments, two or more discrete regions of the first layer are coated with the composition. Each region occupies a predetermined position on the first layer (which can, e.g., correspond to a predetermined position on a substrate on which the first layer is disposed). Two or more discrete monolayer arrays of nanostructures thus remain associated with the coated first layer after deposition of the population of nanostructures on the coated regions of the first layer and removal of nanostructures not associated with the nanostructure association group. Essentially any number of nanostructure arrays can be produced in this manner. For example, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more discrete regions of the first layer can be coated with the composition, whereby 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more discrete monolayer nanostructure arrays are formed at predetermined positions on the first layer.

The regions can be of essentially any desired size. For example, each region (and thus each resulting monolayer array of nanostructures) can have an area of about 10⁴ μm² or less, about 10³ μm² or less, about 10² μm² or less, about 10 μm² or less, about 1 μm² or less, about 10⁵ nm² or less, about 10⁴ nm² or less, or even about 4225 nm² or less, about 2025 nm² or less, about 1225 nm² or less, about 625 nm² or less, or about 324 nm² or less. It will be evident that each of the resulting arrays can, if desired, be incorporated into a transistor or other device.

Techniques useful for coating discrete regions of the first layer have been described in the art. For example, the first layer can be coated with resist (e.g., photoresist), which is exposed and developed in the desired pattern to uncover the desired regions of the first layer, which are then coated with the composition. As another example, the first layer can be coated with the composition, then with resist which is exposed and developed in the inverse of the desired pattern. Composition not protected by the resist is removed, and the remaining resist is removed to leave the composition in the desired regions. As yet another example, the composition can simply be printed on the first layer in desired regions. In another class of embodiments, the monolayer is formed and then patterned, e.g., using resist as described below in the section entitled “Patterning monolayers using resist.”

As noted, the composition used to coat the first layer comprises a nanostructure association group (e.g., a chemical group that can interact, covalently or noncovalently, with a surface of a nanostructure and/or with a ligand coating a surface of a nanostructure). A large number of suitable groups are known in the art and can be adapted to the practice of the present invention. Exemplary nanostructure association groups include, but are not limited to, thiol, amine, alcohol, phosphonyl, carboxyl, boronyl, fluorine or other noncarbon heteroatom, phosphinyl, alkyl, aryl, and like groups.

In one class of embodiments, the composition comprises a silane. For example, the silane can be an organosilane, e.g., a trichlorosilane, trimethoxysilane, or triethoxysilane. As another example, the silane can include a structure having the formula [X₃Si-spacer-nanostructure association group(s)] where X is a Cl, OR, alkyl, aryl, other hydrocarbon, heteroatom, or a combination of these groups, and where the spacer is an alkyl, aryl and/or heteroatom combination. The silane can react with free hydroxyl groups on the surface of a silicon oxide first layer, for example, forming a monolayer coating on the first layer.

In one aspect, the nanostructure association group interacts with a surface of the nanostructures. In one exemplary class of embodiments, the nanostructure association group comprises a thiol group. The coated first layer can thus comprise, e.g., a self-assembled monolayer comprising a thiol compound. The composition can comprise, for example, a mercaptoalkyltrichlorosilane, a mercaptoalkyltrimethoxysilane, or a mercaptoalkyltriethoxysilane, e.g., in which the alkyl group comprises between 3 and 18 carbons (e.g., 12-mercaptododecyltrimethoxysilane). The composition optionally comprises a mixture of two or more different compounds. For example, the composition can include a mixture of a long chain mercaptosilane (e.g., a mercaptoalkyltrichlorosilane, a mercaptoalkyltrimethoxysilane, or a mercaptoalkyltriethoxysilane, where the alkyl group comprises between 8 and 18 carbons) and a short chain mercaptosilane (e.g., a mercaptoalkyltrichlorosilane, a mercaptoalkyltrimethoxysilane, or a mercaptoalkyltriethoxysilane, where the alkyl group comprises 8 or fewer carbons), where the alkyl group in the long chain mercaptosilane comprises at least one more carbon than does the alkyl group in the short chain mercaptosilane. In this example, the ratio of the long and short chain mercaptosilanes can be varied to tailor the surface presented to the nanostructures. For example, the long and short chain mercaptosilanes can be present at a molar ratio of between about 1:10 and about 1:10,000 long chain mercaptosilane to short chain mercaptosilane (e.g., a molar ratio of about 1:100 or 1:1000). As another example, the composition can include a mixture of a long chain mercaptosilane and a short chain silane which need not comprise a nanostructure association group (e.g., an alkyltrichlorosilane, alkyltrimethoxysilane, or alkyltriethoxysilane, where the alkyl group comprises 8 or fewer carbons).

The nanostructures are optionally associated with a surfactant or other surface ligand. In one class of embodiments, each of the nanostructures comprises a coating comprising a ligand associated with a surface of the nanostructure, for example, a silsesquioxane ligand such as those described in Whiteford et al. U.S. Pat. No. 7,267,875 or illustrated in FIG. 3 Panels A-C. The ligands optionally control spacing between adjacent nanostructures in an array. The nanostructure association group can displace the ligand and/or can intercalate between adjacent ligand molecules to reach the surface of the nanostructures.

An exemplary embodiment is schematically illustrated in FIG. 1. In this example, first layer 103 (e.g., a layer of SiO₂) is disposed on substrate 120 (e.g., a silicon substrate). The first layer as depicted is continuously distributed across the substrate, but it will be evident that the first layer can optionally instead be disposed in multiple discrete regions on the substrate. The first layer is coated with composition 104 (e.g., a mixture of long and short chain mercaptosilanes) including nanostructure association group 105 (e.g., a thiol group), to form coated first layer 102 in discrete regions 119. A population of nanostructures 110 (e.g., Pd quantum dots) coated with ligand 111 (e.g., a silsesquioxane ligand) is deposited on the coated first layer, e.g., by spin coating (Panel A). Nanostructures associate with the nanostructure association group, which intercalates among the ligand coating the nanostructures, and form slightly more than a monolayer on the first layer (Panel B). Nanostructures that are not associated with the nanostructure association group are removed (e.g., by washing with a solvent) to leave monolayer arrays 109 of nanostructures associated with the coated first layer (Panel C).

Instead of (or in addition to) displacing or intercalating with the ligand on the nanostructures to interact with the nanostructure surface, the nanostructure association group can interact with the ligand. Thus, in one aspect, each of the nanostructures comprises a coating comprising a ligand associated with a surface of the nanostructure, and the nanostructure association group interacts with the ligand. In some embodiments, the ligand comprises a silsesquioxane. Exemplary ligands include, but are not limited to, those described in U.S. Provisional Patent Application Ser. No. 60/632,570 (supra) or illustrated in FIG. 3 Panels A-C.

The interaction between the ligand and the nanostructure association group can be covalent or noncovalent. Thus, in one class of embodiments, the interaction is noncovalent. The composition can comprise, for example, 3-aminopropyltriethoxysilane (APTES), dodecyltrichlorosilane, octadecyltrichlorosilane (OTS), dodecyltriethoxysilane, octadecyltriethoxysilane, or any of a number of similar compounds. As noted above, the silanes can, e.g., bind to free hydroxyl groups on the surface of an SiO₂ first layer. The dodecyl and octadecyl groups provide a hydrophobic surface, e.g., for interaction with a hydrophobic ligand on the nanostructures, while APTES provides a polar surface, e.g., for interaction with a ligand that can hydrogen bond with the APTES amino groups.

In another class of embodiments, the nanostructure association group forms a covalent bond with the ligand. The composition is optionally photoactivatable, such that the covalent bond between the ligand and the nanostructure association group is formed only upon exposure to light. In such embodiments, the methods include exposing one or more discrete regions of the coated first layer, each of which occupies a predetermined position on the coated first layer, to light.

Essentially any number of nanostructure arrays can be produced in this manner. For example, two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more discrete regions of the coated first layer can be exposed to the light, resulting in formation of a like number of discrete nanostructure monolayer arrays at predetermined positions on the first layer (and thus, at predetermined positions on any substrate on which the first layer is disposed). Similarly, the regions can be of essentially any desired size. For example, each region (and thus each resulting monolayer array of nanostructures) can have an area of about 10⁴ μm² or less, about 10³ μm² or less, about 10² μm² or less, about 10 μm² or less, about 1 μm² or less, about 10⁵ nm² or less, about 10⁴ nm² or less, or even about 4225 nm² or less, about 2025 nm² or less, about 1225 nm² or less, about 625 nm² or less, or about 324 nm² or less. It will be evident that each of the resulting arrays can, if desired, be incorporated into a transistor or other device. Using a photoactivatable composition thus provides a convenient means of patterning, such that a desired number, size, and/or shape of monolayer nanostructure array(s) can be produced.

A large number of photoactivatable compounds are known in the art and can be adapted to the practice of the present invention. For example, the composition can include a phenyl azide group, which when photoactivated can form a covalent bond with, e.g., a silsesquioxane ligand comprising a coating associated with a surface of the nanostructures. Exemplary photoactivatable compositions include, but are not limited to, compounds comprising an aryl azide group (e.g., a phenyl azide, hydroxyphenyl azide, or nitrophenyl azide group), a psoralen, or a diene.

The composition can be applied to form the coating in one or more steps. For example, in certain embodiments, coating the first layer with the composition involves coating the first layer with a first compound and then coating the first layer with a second compound which interacts with the first compound and which includes the nanostructure association group. For example, the first layer (e.g., an SiO₂ first layer) can be coated with 3-aminopropyltriethoxysilane (APTES) as the first compound and then with N-5-azido-2-nitrobenzoyloxysuccinimide (ANB-NOS) as the second compound. (ANB-NOS has an amine-reactive N-hydroxysuccinimide ester group, which reacts with the APTES amino groups, and a nitrophenyl azide group, which can be photolyzed, e.g., at 320-350 nm.)

An exemplary embodiment is schematically illustrated in FIG. 2. In this example, first layer 203 (e.g., a layer of SiO₂) is disposed on substrate 220 (e.g., a silicon substrate). The first layer is coated with composition 204 (e.g., APTES and ANB-NOS), which includes photoactivatable nanostructure association group 205 (e.g., a phenyl azide group), to form coated first layer 202 (Panel A). A population of nanostructures 210 (e.g., Pd quantum dots) coated with ligand 211 (e.g., a silsesquioxane ligand) is deposited on the coated first layer, e.g., by spin coating to form slightly more than a monolayer (Panel B). Discrete regions 219 of the coated first layer are exposed to light 230, while the remainder of the coated first layer is protected from exposure to the light by mask 231 (Panel C). Nanostructures that are not covalently bonded to the nanostructure association group are removed (e.g., by washing with a solvent, e.g., hexane) to leave monolayer arrays 209 of nanostructures associated with the coated first layer (Panel D).

In one class of embodiments, the population of nanostructures is deposited on the coated first layer by depositing a solution comprising the nanostructures dispersed in at least one solvent on the coated first layer. The solution of nanostructures can be deposited by essentially any convenient technique, for example, spin coating, dip coating, soaking, spraying, or similar techniques. The solvent can, but need not be, partially or completely removed from the deposited nanostructures, e.g., by evaporation. Any nanostructures which are not associated with the nanostructure association group can be conveniently removed, e.g., by washing with at least one solvent.

In one aspect, the monolayer array (or each of multiple arrays) of nanostructures formed by the methods comprises an ordered array, e.g., a hexagonal-close packed monolayer array comprising substantially spherical nanocrystals or a square array comprising cubic nanocrystals. For many applications, however, an ordered array is not required. For example, for an array for use in a memory device, the nanostructures need not be ordered in the array as long as they achieve sufficient density in a disordered array. Thus, in another aspect, the monolayer array of nanostructures comprises a disordered array.

In one class of embodiments, the array (or each of multiple arrays produced by the methods) has a high density of nanostructures. For example, the monolayer array of nanostructures optionally has a density greater than about 1×10¹⁰ nanostructures/cm², greater than about 1×10¹¹ nanostructures/cm², greater than about 1×10¹² nanostructures/cm², or even greater than about 1×10¹³ nanostructures/cm².

In one class of embodiments, the nanostructures comprise substantially spherical nanostructures or quantum dots. The nanostructures can comprise essentially any desired material, chosen, e.g., based on the use to which the resulting monolayer array of nanostructures is to be put. For example, the nanostructures can comprise a conductive material, a nonconductive material, a semiconductor, and/or the like. In one aspect, the nanostructures have a work function of about 4.5 eV or higher. Such nanostructures are useful, for example, in fabrication of memory devices, where if the work function of the nanostructures is not sufficiently high, electrons stored in the nanostructures tend to travel back across the tunnel dielectric layer, resulting in memory loss. Thus, the nanostructures (e.g., the substantially spherical nanostructures or quantum dots) optionally comprise materials such as palladium (Pd), iridium (Ir), nickel (Ni), platinum (Pt), gold (Au), ruthenium (Ru), cobalt (Co), tungsten (W), tellurium (Te), iron platinum alloy (FePt), or the like. Nanostructures are described in greater detail below in the section entitled “Nanostructures”.

Devices produced by or useful in practicing the methods of the invention are also a feature of the invention. Thus, another general class of embodiments provides a device including a coated first layer and a monolayer array of nanostructures disposed on the coated first layer. The coated first layer includes a first layer coated with a composition comprising a nanostructure association group, and the nanostructures are associated with the nanostructure association group.

Essentially all of the features noted for the methods above apply to these embodiments as well, as relevant; for example, with respect to composition of the first layer, substrate, composition used to coat the first layer, nanostructure association group, and nanostructures. It is worth noting that the monolayer array of nanostructures can comprise an ordered array or a disordered array, and that the coated first layer optionally comprises two or more discrete regions, each of which occupies a predetermined position (so the device optionally includes two or more monolayer arrays of nanostructures disposed on the coated first layer). It is also worth noting that the device optionally comprises a flash transistor (floating gate memory MOSFET) or memory device. Thus, in certain embodiments, the first layer comprises a dielectric material, such as an oxide (e.g., a metal oxide, silicon oxide, hafnium oxide, or alumina (Al₂O₃)), a nitride, an insulating polymer, or another nonconductive material. In this class of embodiments, the first layer (which serves as a tunnel dielectric layer) is preferably thin (e.g., has a thickness of between about 1 nm and about 10 nm, e.g., between 3 and 4 nm), and is disposed on a substrate that comprises a semiconductor (e.g., a Si substrate). The substrate typically includes a source region, a drain region, and a channel region between the source and drain regions and underlying the monolayer array of nanostructures. A control dielectric layer is disposed on the monolayer array of nanostructures, and a gate electrode is disposed on the control dielectric layer. The control dielectric layer comprises a dielectric material, e.g., an oxide (e.g., a metal oxide, SiO₂, or Al₂O₃), an insulating polymer, or another nonconductive material. The electrodes can comprise essentially any suitable material(s). For example, the gate electrode can comprise polysilicon, a metal silicide (e.g., nickel silicide or tungsten silicide), ruthenium, ruthenium oxide, or Cr/Au. Similarly, the source and drain electrodes optionally comprise a metal silicide (e.g., nickel silicide or tungsten silicide) or any of various barrier metals or metal nitrides such as TiN, connecting to other metals such as copper or aluminum.

An exemplary embodiment is schematically illustrated in FIG. 1 Panel C. In this example, device 101 includes coated first layer 102 and monolayer arrays 109 of nanostructures 110 disposed on the coated first layer in discrete regions 119. Coated first layer 102 includes first layer 103 coated with composition 104 including nanostructure association group 105. The first layer is disposed on substrate 120.

A related exemplary embodiment is schematically illustrated in FIG. 2 Panel D. In this example, device 201 includes coated first layer 202 and monolayer arrays 209 of nanostructures 210 disposed on the coated first layer in discrete regions 219. Coated first layer 202 includes first layer 203 coated with composition 204 including nanostructure association group 205. The first layer is disposed on substrate 220. In this embodiment, nanostructure association group 205 is covalently bonded to ligand 211 on the nano structures.

Monolayer Formation in Spin-on-Dielectrics

As noted above, nanostructure monolayers are desirable for a number of applications. For example, formation of quantum dot monolayers on tunnel oxides is desirable for production of nanocrystal flash memory devices. Because the performance of nanocrystal based flash memory devices (or other nanostructure-based devices) can be determined at least in part by variations in nanostructure density, high density monolayers with low nanostructure density variations are desired. However, since imperfect size distribution of the nanodots affects coherent length of self-assembly, simply coating a substrate with dots (e.g., a substrate whose surface is not modified with a composition that includes a nanostructure association group and where the dots are not dispersed in a matrix material, etc.) typically results in localized dot assemblies with grain boundary formed among them. Since the coherent self-assembly length depends on the size distribution of the dots, the quality of the assembly process has been limited by the size distribution of the dots and it has been challenging to improve the quality of the resulting assemblies. Solution phase chemistry usually provides size distributions of less than 10%, while the conventional CVD and PVD approaches provide grain distributions of about 20% to 25%.

One aspect of the invention provides methods that facilitate randomized assembly of nanostructures (e.g., quantum dots) without grain boundary formation by using spin-on-dielectric materials. The nanostructures are dispersed well in a solution in the presence of a spin-on-dielectric (e.g., spin-on-glass) material. When the nanostructure solution is spun onto a substrate, the nanostructures form a randomized monolayer assembly in the spin-on-dielectric material. The spin-on-dielectric material forms a matrix on the substrate after the coating process; the nanostructures are randomly distributed in the matrix. The nanostructure density in the resulting array is controlled by their concentration in the solution. Variation in nanostructure density across the resulting monolayer is minimal.

Accordingly, one general class of embodiments provides methods for forming a nanostructure array. In the methods, a first layer is provided, as are nanostructures dispersed in a solution comprising a liquid form of a spin-on-dielectric. The solution is disposed on the first layer, whereby the nanostructures form a monolayer array on the first layer. The liquid form of the spin-on-dielectric is then cured to provide a solid form of the spin-on-dielectric. The monolayer array of nanostructures is embedded in the resulting solid spin-on-dielectric matrix.

Suitable materials for the first layer have been described above; examples include, but are not limited to, a semiconductor or a dielectric material such as an oxide (e.g., a metal oxide, silicon oxide, hafnium oxide, or alumina (Al₂O₃), or a combination of such oxides) or a nitride (e.g., silicon nitride). The first layer is optionally treated prior to disposition of the solution. For example, the first layer can be coated with hexamethyldisilizane (HMDS) or a silane before the solution is disposed on it. Thus, for example, the first layer can comprise silicon oxide or silicon nitride coated with HMDS. The first layer is optionally disposed on a substrate, e.g., a substrate comprising a semiconductor. In one class of embodiments, the first layer has a thickness of between about 1 nm and about 10 nm, e.g., between 3 and 4 nm. The substrate can include a source region, a drain region, and a channel region between the source and drain regions and underlying the monolayer array of nanostructures, and the methods include disposing a gate electrode on the solid form of the spin-on-dielectric material. Optionally, the thickness of the control dielectric is increased by disposing a dielectric layer on the solid form of the spin-on-dielectric, prior to disposing the gate electrode on the solid form of the spin-on-dielectric material. As noted above, preferred tunnel and control dielectrics and gate electrodes are described in Chen U.S. Patent Publication No. 2008/0150009 and Duan et al. U.S. Pat. No. 8,030,161, respectively.

The solution including the nanostructures and the liquid spin-on-dielectric can be disposed on the first layer by essentially any convenient technique. For example, the first layer can be spin coated with the solution.

A large number of spin-on-dielectric materials are known in the art and can be adapted to the methods. As just a few examples, the solid form of the spin-on-dielectric can comprise silicon oxide, aluminum oxide, hafnium oxide (e.g., HfO₂), lanthanum oxide (e.g., La₂O₃), or tantalum oxide (e.g., Ta₂O₅). Similarly, the liquid form of the spin-on-dielectric can comprise aluminum i-propoxide (Al i-propoxide), tri-methyl aluminum, tri-ethyl aluminum, hafnium t-butoxide (Hf t-butoxide), hafnium ethoxide (Hf ethoxide), tetrabenzyl hafnium (tetrabenzyl Hf), tris(cyclopentadienyl)lanthanum, tris(i-propylcyclopentadienyl)lanthanum, pentakis(dimethylamino)tantalum, tantalum methoxide (Ta methoxide), or tantalum ethoxide (Ta ethoxide). As noted herein, the solid form of the spin-on-dielectric optionally serves as a diffusion barrier.

In one class of embodiments, the spin-on-dielectric is a spin-on-glass. The liquid form of the spin-on-glass can comprise a silicon compound that forms a silicon oxide (e.g., SiO₂) after curing. For example, the liquid form of the spin-on-glass can include a silsesquioxane, e.g., mercapto-propyl-cyclohexyl polyhedral oligomeric silsesquioxane (see FIG. 3 Panel A, where R is a cyclohexyl group), hydrogen silsesquioxane, methyl silsesquioxane, octavinyl dimethyl silyl silsesquioxane, octasilane silsesquioxane, octavinyl-T8 silsesquioxane, aminopropylcyclohexyl polyhedral oligomeric silsesquioxane (aminopropylcyclohexyl POSS, see FIG. 3 Panel C, where R is a cyclohexyl group; commercially available from Hybrid Plastics, Inc.), acrylo silsesquioxane (e.g., an acrylo POSS® cage mixture commercially available from Hybrid Plastics, Inc., that includes (C₆H₉O₂)_(n)(SiO_(1.5))_(n) where n=8, 10, 12; n=8 is shown in FIG. 3 Panel E), or methacrylo silsesquioxane (e.g., a methacryl POSS® cage mixture commercially available from Hybrid Plastics, Inc., that includes (C₇H₁₁O₂)_(n)(SiO_(1.5))_(n) where n=8, 10, 12; n=8 is shown in FIG. 3 Panel D), or a combination thereof (e.g., a combination of silsesquioxanes with and without a nanostructure binding moiety that can bind to the surface of the nanostructures, e.g., a mixture of mercapto-propyl-cyclohexyl POSS and hydrogen silsesquioxane). A variety of such silsesquioxanes are known in the art, and a number are commercially available, e.g., from Gelest, Inc. Other types of spin-on-glass materials can also be used. Preferred spin-on-glass or spin-on-dielectric materials are ones which dissolve well in the solvent for the nanostructures and produce good wetting behavior on the relevant surface (e.g., on an HMDS modified tunnel oxide layer).

The spin-on-dielectric material can be cured as is known in the art, for example, by UV, electron beam, heat, or the like. In one class of embodiments, the liquid form of the spin-on-dielectric comprises a photopolymerizable compound (e.g., hydrogen silsesquioxane or octavinyl-T8 silsesquioxane or another photopolymerizable silsesquioxane or silicate). Use of a photopolymerizable spin-on-dielectric facilitates patterning of the monolayer array, as described in greater detail below in the section entitled “Patterning monolayers using resist.” In brief, to pattern the array, a predetermined pattern is exposed to light to cure the spin-on-dielectric, and uncured material along with its embedded nanostructures is removed.

Thus, in one class of embodiments, at least a first region of the first layer and the solution disposed thereon are exposed to light of an appropriate wavelength, thereby curing the spin-on-dielectric in the first region. Simultaneously, at least a second region of the first layer and the solution disposed thereon are protected from the light, whereby the spin-on-dielectric in the second region remains uncured. The uncured spin-on-dielectric and the nanostructures therein are then removed from the first layer without removing the cured spin-on-dielectric and the nanostructures therein, leaving one or more monolayer arrays on the first layer. The position and size of the array(s) in the cured spin-on-dielectric matrix correspond to that of the first region(s).

The methods can be used to produce essentially any number of monolayer arrays. For example, two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, or even 1×10¹² or more discrete regions of the first layer and the solution disposed thereon can be exposed to the light, such that a like number of discrete nanostructure monolayer arrays remains on the first layer.

Similarly, if such patterning is desired when the spin-on-dielectric is not conveniently photopolymerizable, a photoresist (e.g., any well-established photoresist) can be included in the solution with the nanostructures and the liquid form of the spin-on-dielectric. The percentage of the various components are adjusted as desired, e.g., to provide adequate photo-curing of the matrix and a good dielectric after curing.

The monolayer array of nanostructures is typically a disordered array. The array (or each of multiple arrays) produced by the methods optionally has a high density of nanostructures. For example, the monolayer array of nanostructures optionally has a density greater than about 1×10¹⁰ nanostructures/cm², greater than about 1×10¹¹ nanostructures/cm², greater than about 1×10¹² nanostructures/cm², or even greater than about 1×10¹³ nanostructures/cm². As noted, variation in the density of the nanostructures across the array (or over large areas of the array, e.g., areas 2-3 micrometers on a side) is preferably low. For example, variation in density of the nanostructures in the monolayer array can be less than 10% across the monolayer, e.g., less than 5%.

Essentially all of the features noted for the embodiments above apply to these embodiments as well, as relevant; for example, with respect to disposition of the first layer on a substrate, composition of the substrate, incorporation of the array(s) into transistor(s), nanostructure shape and composition, nanostructure ligands, size of the array(s), and the like. For example, the nanostructures are optionally substantially spherical nanostructures or quantum dots. The nanostructures can comprise essentially any desired material. In one class of embodiments, the nanostructures have a work function of about 4.5 eV or higher. For example, the nanostructures can comprise palladium, platinum, nickel, or ruthenium.

Monolayer formation of Pd, Ru, and Ni quantum dots is illustrated in FIG. 8 Panels A-C, respectively. In these examples, the substrate was coated with HMDS, and mercapto-propyl-cyclohexyl polyhedral oligomeric silsesquioxane (3.5 mg/ml in chlorobenzene or xylene) was used as the spin-on-glass material. In these examples, a silicon nitride membrane was used as the substrate; other exemplary substrates include, e.g., an SiO₂ wafer or oxynitride substrate. The silsesquioxane was cured in an O₂, CDA environment, by ramping to 300-400° C. and dwelling at the high temperature for 5-30 minutes.

As noted, devices produced by or useful in practicing the methods of the invention are also a feature of the invention. Thus, another general class of embodiments provides a device including a first layer, a liquid or solid form of a spin-on-dielectric disposed on the first layer, and a monolayer of nanostructures disposed on the first layer in the spin-on-dielectric.

Essentially all of the features noted for the methods above apply to these embodiments as well, as relevant; for example, with respect to composition of the liquid and/or solid form of the spin-on-dielectric, first layer, substrate, and nanostructures. It is worth noting that the monolayer of nanostructures is typically a disordered monolayer, and that the device optionally comprises two or more discrete monolayer arrays embedded in the solid form of the spin-on-dielectric, each of which typically occupies a predetermined position. It is also worth noting that the device optionally comprises a flash transistor (floating gate memory MOSFET) or memory device. Thus, in certain embodiments, the first layer comprises a dielectric material, such as an oxide (e.g., a metal oxide, silicon oxide, hafnium oxide, or alumina (Al₂O₃)), a nitride, an insulating polymer, or another nonconductive material. In this class of embodiments, the first layer (which serves as a tunnel dielectric layer) is preferably thin (e.g., has a thickness of between about 1 nm and about 10 nm, e.g., between 3 and 4 nm), and is disposed on a substrate that comprises a semiconductor (e.g., a Si substrate). The substrate typically includes a source region, a drain region, and a channel region between the source and drain regions and underlying the monolayer array of nanostructures. A control dielectric layer is disposed on the monolayer of nanostructures in the spin-on-dielectric, if needed, and a gate electrode is disposed on the control dielectric layer. The control dielectric layer comprises a dielectric material, e.g., an oxide (e.g., a metal oxide, SiO₂, or Al₂O₃), an insulating polymer, or another nonconductive material. The electrodes can comprise essentially any suitable material(s). For example, the gate electrode can comprise polysilicon, a metal silicide (e.g., nickel silicide or tungsten silicide), ruthenium, ruthenium oxide, or Cr/Au. Similarly, the source and drain electrodes optionally comprise a metal silicide (e.g., nickel silicide or tungsten silicide) or any of various barrier metals or metal nitrides such as TiN, connecting to other metals such as copper or aluminum.

Solvent Annealing

One aspect of the invention provides solvent annealing methods that can be used to improve monolayer quality. Quantum dots or other nanostructures are deposited on a surface, and solvent annealing is then employed: the nanostructures are exposed to solvent vapor, introducing some short-range mobility to the nanostructures on the surface and thus allowing monolayer assembly quality to improve.

Accordingly, one general class of embodiments provides methods for forming a nanostructure array. In the methods, a first layer is provided and a population of nanostructures is deposited on the first layer. The nanostructures deposited on the first layer are exposed to extrinsic solvent vapor, whereby the nanostructures assemble into a monolayer array.

To expose the nanostructures on the first layer to the solvent vapor, a first solvent can be provided in liquid form (e.g., in a reservoir physically distinct from the first layer). The first layer bearing the nanostructures is typically placed in a container, e.g., a closed container, with the liquid first solvent. The first solvent (and the first layer) can be maintained at ambient temperature, but optionally the first solvent is heated, e.g., to a temperature sufficient to vaporize at least a portion of the solvent. For example, the first solvent can be heated to a temperature greater than 30° C., greater than 50° C., greater than 70° C., or greater than 90° C. Preferably, this temperature is less than the boiling point of the solvent and is not so high as to result in fusion of the nanostructures with each other. It will be evident that heating can both vaporize the solvent and permit the nanostructures on the surface to have greater mobility. The selected temperature is maintained for a sufficient time to permit monolayer formation. The first solvent is preferably one in which the nanostructures disperse well and that wets the first layer well. Suitable solvents include, but are not limited to, hexane, octane, xylene, chlorobenzene, methyl-isobutylketone (MIBK), and volatile siloxanes.

The nanostructures can be deposited on the first layer by dispersing them in a solution comprising at least one second solvent and disposing the resulting solution on the first layer. The solution comprising the nanostructures can be applied to the first layer by essentially any technique known in the art, for example, spray coating, flow coating, capillary coating, dip coating, roll coating, ink-jet printing, spin coating, or other wet coating techniques. Optionally, the solution is disposed on the first layer by a technique other than spin coating. The second solvent in which the nanostructures are dispersed can be the same as or different from the first solvent to whose vapor the nanostructures are exposed after deposition on the first layer.

The nanostructures are optionally substantially dry when exposed to the solvent vapor. Thus, in one class of embodiments, the methods include evaporating the second solvent in which the nanostructures were dispersed to provide dry nanostructures deposited on the first layer, after disposing the solution on the first layer and prior to exposing the nanostructures to the solvent vapor. The dry nanostructures deposited on the first layer are optionally exposed to air or to a selected atmosphere (e.g., an oxygen-containing atmosphere, N₂, CDA (compressed dry air), or the like), typically at ambient temperature, prior to exposing the nanostructures to the solvent vapor.

In another class of embodiments, the nanostructures are still wet with the second solvent when they are exposed to the solvent vapor. For example, a thin film of second solvent can be permitted to remain on the first layer surrounding the nanostructures. In these embodiments, exposure to the solvent vapor of the first solvent decreases the evaporation rate of the second solvent from the surface, facilitating assembly of the nanostructures.

The solvent vapor is extrinsically supplied, and thus arises from a source of first solvent extrinsic to the nanostructures and typically the first layer. For example, the solvent vapor does not arise from a film of second solvent remaining on the first layer and surrounding the nanostructures.

In one class of embodiments, the number of nanostructures applied to the first layer is substantially equal to the number of nanostructures desired in the resulting monolayer array. Since excess nanostructures need not be applied, a washing step to remove excess nanostructures after monolayer formation is not required.

As for the other embodiments described herein, the first layer can comprise essentially any desired material, e.g., a conductive material, a nonconductive material, a semiconductor, or the like, including, for example, a silicon wafer or a flexible material such as a plastic. The first layer optionally comprises a dielectric material such as an oxide or nitride, e.g., silicon oxide, hafnium oxide, alumina, or silicon nitride, and is optionally disposed on a substrate (in embodiments in which it is not serving as a substrate).

The first layer can be modified before deposition of the nanostructures, for example, with a compound that forms a self-assembled monolayer. Exemplary compounds include, but are not limited to, a mercaptosilane, APTES, OTS, and HMDS.

The resulting monolayer array of nanostructures can comprise an ordered array or a disordered array. The array optionally has a density greater than about 1×10¹⁰ nanostructures/cm², greater than about 1×10¹¹ nanostructures/cm², greater than about 1×10¹² nanostructures/cm² (e.g., 3−4×10¹² nanostructures/cm²), or greater than about 1×10¹³ nanostructures/cm².

Essentially all of the features noted for the embodiments above apply to these embodiments as well, as relevant; for example, with respect to incorporation of the array(s) into transistor(s), nanostructure shape and composition, nanostructure ligands, size of the array(s), and the like. For example, the nanostructures are optionally substantially spherical nanostructures or quantum dots. The nanostructures can comprise essentially any desired material. In one class of embodiments, the nanostructures have a work function of about 4.5 eV or higher.

FIG. 9 presents micrographs of Pd quantum dots deposited on low stress silicon nitride before (Panel A) and after (Panel B) solvent annealing. In this example, chlorobenzene is utilized as the annealing solvent. The solvent is heated to 110° C. for 12 hours, during which the dots on substrate are exposed to the chlorobenzene vapor. The solvent annealing process decreased the percentage of multi-layer regions and improved the assembly quality.

Monolayer formation is, as noted above, an important step in fabricating any of a number of nanostructure-based devices, including quantum dot-based devices. Current techniques for forming quantum dot monolayers typically use an excess of the dots. For example, when a wafer is spin coated with quantum dots, most of the dots are spun away into the chemical drain (typically, more than 95% of the dots). These excess dots cannot generally be recovered for reuse due to concerns about contamination and quality control. Techniques that minimize dot consumption are thus desirable, particularly for mass production of nanostructure devices.

One aspect of the invention provides methods that facilitate monolayer formation while optionally minimizing consumption of nanostructures. The surface of interest (e.g., a wafer) is coated with quantum dots or other nanostructures. The surface can be spin-coated with dots, or optionally the dots can be applied to the surface with a non-spinning technique. The dots can be applied to the surface in an amount calculated to produce a desired density when the dots are in a monolayer on the surface. To obtain a high-quality monolayer, solvent annealing is employed after deposition of the dots: the dots are exposed to solvent vapor, giving them short-range mobility and permitting them to move from multi-layer regions to form a monolayer.

Patterning Monolayers Using Resist

Certain methods described above permit the size, shape, and/or position of resultant monolayer nanostructure arrays to be predetermined Use of resist, e.g., photoresist, can also facilitate such patterning of monolayer arrays.

One general class of embodiments provides methods for patterning a nanostructure monolayer. In the methods, a monolayer of nanostructures disposed on a first layer is provided. Resist is disposed on the monolayer of nanostructures to provide a resist layer, and a predetermined pattern on the resist layer is exposed (e.g., to light, an electron beam, x-rays, etc.), to provide exposed resist in at least a first region of the resist layer and unexposed resist in at least a second region of the resist layer. If a positive resist is utilized, the exposed resist and its underlying nanostructures are removed, and then the unexposed resist is removed without removing its underlying nanostructures from the first layer. If instead a negative resist is utilized, the unexposed resist and its underlying nanostructures are removed, and then the exposed resist is removed without removing its underlying nanostructures. Whether positive or negative resist is used, at least one nanostructure monolayer array defined by the first region remains on the first layer. It will be evident that if a positive resist is used, the position of the array corresponds to that of the second region (i.e., the inverse of the first region), while if a negative resist is used, the position of the array corresponds to that of the first region. The boundaries of the nanostructure monolayer array are thus defined by the boundaries of the first region.

The monolayer of nanostructures can be produced by any convenient technique. For example, the first layer can be spin coated with a solution of nanostructures, and any nanostructures which are not in contact with the first layer can then be removed, e.g., by washing. Monolayers can also be formed, e.g., by soaking or dip coating the first layer or by using a commercially available Langmuir-Blodgett device.

The first layer can, but need not, include a coating comprising a nanostructure association group such as those described above, e.g., to increase adherence of the nanostructures to the first layer. Similarly, the nanostructures optionally comprise a ligand such as those described above.

The resist can be disposed (e.g., by spin coating or other techniques known in the art) directly on the monolayer of nanostructures. Alternatively, one or more additional layers can be disposed between the resist and the monolayer. For example, in one class of embodiments, a dielectric layer is disposed on the monolayer of nanostructures, and the resist is disposed on the dielectric layer.

The methods can be used to produce essentially any number of monolayer arrays. For example, when positive resist is used, the unexposed resist can be provided in two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more discrete second regions of the resist layer, such that two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more discrete nanostructure monolayer arrays remain on the first layer. Similarly, when negative resist is used, exposed resist can be provided in two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more discrete first regions of the resist layer, such that a like number of discrete nanostructure monolayer arrays remains on the first layer.

Essentially all of the features noted for the methods above apply to these embodiments as well, as relevant; for example, with respect to composition of the first layer, disposition of the first layer on a substrate, composition of the substrate, incorporation of the array(s) into transistor(s), nanostructure shape and composition, size and density of the array(s), and the like. It is worth noting that the monolayer array (or each of multiple arrays) can comprise an ordered array or a disordered array.

An exemplary embodiment is schematically illustrated in FIG. 4. In this example, first layer 420 (e.g., a 3-4 nm thick layer of SiO₂ or another oxide, nitride, or other nonconductive material) is disposed on substrate 421 (e.g., a Si or other semiconductor substrate). In step 401, monolayer 422 of nanostructures (e.g., Pd quantum dots) is disposed on the first layer. In step 402, control dielectric layer 423 (e.g., an oxide such as SiO₂ or Al₂O₃, an insulating polymer, or another nonconductive material) is disposed on the monolayer. (For example, an Al₂O₃ layer can be disposed by atomic layer deposition, or an SiO₂ layer can be disposed by chemical vapor deposition.) The control dielectric layer is coated with a positive resist in step 403, masked and exposed in step 404, and developed in step 405 to remove the exposed resist. In steps 406-408, source region 430 and drain region 431, which are separated by channel region 437, are created in substrate 421 by ion implantation (step 406), stripping off the unexposed resist (step 407), and activation (step 408). The control dielectric layer is again coated with positive resist (e.g., polymethyl methacrylate (PMMA)) to form resist layer 432, in step 409. In photolithography step 410, resist in first regions 433 is exposed (e.g., by electron beam or deep UV), while resist in second region 434 is protected by mask 435 and remains unexposed. Exposed resist is removed in step 411 (e.g., developed with an organic solvent), then the portion of the control dielectric layer and first layer and the nanostructures underlying the exposed resist in first region 433 are removed (e.g., by dipping in hydrofluoric acid) in step 412, leaving monolayer array of nanostructures 445. The boundaries of array 445 correspond to those of second region 434, and are therefore defined by those of first region 433. In step 413, a metal layer is disposed to form source electrode 440 and drain electrode 441. In step 414, the unexposed resist is removed without disturbing the control dielectric layer or the nanostructures underlying it (e.g., by contacting the unexposed resist with at least one solvent, e.g., acetone). Gate electrode 442 (e.g., Cr/Au or another suitable material, including, but not limited to, polysilicon, a metal silicide (e.g., nickel silicide or tungsten silicide), ruthenium, or ruthenium oxide) is then disposed on the control dielectric layer in step 415, producing transistor 450.

Another general class of embodiments also provides methods for patterning a nanostructure monolayer. In the methods, a first layer comprising a resist layer disposed thereon is provided. The resist is permitted to remain in at least a first region of the resist layer while the resist is removed from at least a second region of the resist layer. A population of nanostructures is disposed on the resist layer and the first layer; the nanostructures contact the resist in the first region and the first layer in a second region. The resist and its overlying nanostructures are removed from the first region, and any nanostructures which are not in contact with the first layer are removed from the second region, leaving at least one nanostructure monolayer array remaining on the first layer. It will be evident that the position, size, shape, etc., of the array corresponds to that of the second region, and that the number of arrays formed is equal to the number of second regions.

The resist can disposed, exposed, and removed according to lithography techniques well known in the art. Removal of the resist and its overlying nanostructures from the first region and of any nanostructures which are not in contact with the first layer (e.g., in the second region) is optionally accomplished simultaneously, for example, by washing with at least a first solvent.

Essentially all of the features noted for the methods above apply to these embodiments as well, as relevant; for example, with respect to composition of the first layer, coating of the first layer, disposition of the first layer on a substrate, composition of the substrate, incorporation of the array(s) into transistor(s), nanostructure shape and composition, nanostructure ligands, size and density of the array(s), and the like. It is worth noting that the monolayer array (or each of multiple arrays) can comprise an ordered array or a disordered array.

Yet another general class of embodiments also provides methods for patterning a nanostructure monolayer. In the methods, resist and a monolayer of nanostructures embedded in the resist are disposed on a first layer, to provide a resist layer. A predetermined pattern on the resist layer is exposed (e.g., to light, an electron beam, x-rays, etc.), to provide exposed resist in at least a first region of the resist layer and unexposed resist in at least a second region of the resist layer. If a positive resist is employed, the exposed resist and its embedded nanostructures are removed from the first layer without removing the unexposed resist and its embedded nanostructures. If a negative resist is employed, the unexposed resist and its embedded nanostructures are removed from the first layer without removing the exposed resist and its embedded nanostructures. Whether positive or negative resist is used, at least one nanostructure monolayer array defined by the first region remains on the first layer. It will be evident that if a positive resist is used, the position of the array corresponds to that of the second region (i.e., the inverse of the first region), while if a negative resist is used, the position of the array corresponds to that of the first region. The boundaries of the nanostructure monolayer array are thus defined by the boundaries of the first region.

The resist layer can be formed by essentially any convenient technique. For example, the first layer can be spin coated with a solution comprising the resist and the nanostructures.

The methods can be used to produce essentially any number of monolayer arrays. For example, when positive resist is used, the unexposed resist can be provided in two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more discrete second regions of the resist layer, such that two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more discrete nanostructure monolayer arrays remain on the first layer. Similarly, when negative resist is used, exposed resist can be provided in two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more discrete first regions of the resist layer, such that a like number of discrete nanostructure monolayer arrays remains on the first layer.

In one aspect, the resist comprises a silicon compound, and the exposed resist optionally comprises silicon oxide (e.g., SiO₂). For example, the resist can be a silsesquioxane, such as mercapto-propyl-cyclohexyl polyhedral oligomeric silsesquioxane, hydrogen silsesquioxane, methyl silsesquioxane, octavinyl dimethyl silyl silsesquioxane, octasilane silsesquioxane, octavinyl-T8 silsesquioxane, aminopropylcyclohexyl polyhedral oligomeric silsesquioxane, acrylo silsesquioxane, or methacrylo silsesquioxane, or a combination thereof. In one class of embodiments, the silsesquioxane or silicate is photopolymerizable. The nanostructures can, but need not, have a silsesquioxane or other ligand such as those noted herein bound to their surface.

Essentially all of the features noted for the methods above apply to these embodiments as well, as relevant; for example, with respect to composition of the first layer, treatment of the first layer, disposition of the first layer on a substrate, composition of the substrate, incorporation of the array(s) into transistor(s), nanostructure shape and composition, size and density of the array(s), and the like. It is worth noting that the monolayer array (or each of multiple arrays) can comprise an ordered array or, typically, a disordered array.

The resist layer optionally includes a compound that increases the dielectric constant of the layer. For example, the resist layer can include a spin-on-dielectric (e.g., a compound such as aluminum i-propoxide, tri-methyl aluminum, tri-ethyl aluminum, hafnium t-butoxide, hafnium ethoxide, tetrabenzyl hafnium, tris(cyclopentadienyl) lanthanum, tris(i-propylcyclopentadienyl)lanthanum, pentakis(dimethylamino)tantalum, tantalum methoxide, or tantalum ethoxide) along with a negative resist (e.g., hydrogen silsesquioxane), such that when the resist is exposed and the spin-on-dielectric is cured, the resulting matrix around the nanostructures has a dielectric constant higher than that of exposed resist without the compound. The nanostructures are optionally adjacent to or in physical or electrical contact with the first layer, or optionally are completely surrounded by the resist. The resist layer can also be utilized as a diffusion barrier, e.g., to prevent the material comprising the nanostructures from diffusing into the first layer or any underlying substrate during a subsequent high temperature processing step. For example, when metal nanostructures on an SiO₂ first layer are annealed at elevated temperatures, the metal can diffuse through the SiO₂ layer. With a high k dielectric layer in the middle of metal nanostructures and the substrate, the diffusion can be blocked. As just one example, a hafnium oxide-containing resist can help stabilize Ru nanostructures during an annealing step.

An exemplary embodiment is schematically illustrated in FIG. 10. In this example, in step 1001, resist 1024 and nanostructures 1023 are disposed on first layer 1020 to provide resist layer 1022. In step 1002, resist in first regions 1033 is exposed (e.g., by deep UV), while resist in second regions 1034 is protected by mask 1035 and remains unexposed. Unexposed resist with its embedded nanostructures is removed (e.g., developed with an organic solvent) in step 1003, leaving monolayer arrays 1045 of nanostructures embedded in exposed resist.

FIG. 11 presents micrographs illustrating monolayer arrays patterned into the Nanosys, Inc. logo and the word “nano” using methods of the invention. A silicon nitride membrane was spin coated with a solution of ruthenium nanodots and aminopropylcyclohexyl POSS (see FIG. 3 Panel C, where R is a cyclohexyl group) in xylene to obtain a monolayer of Ru dots embedded in the aminopropylcyclohexyl POSS. The monolayer was then subjected to electron beam patterning with the first regions (forming the logo and “nano”) exposed to electron beam with beam intensity 400 μC/cm². The unexposed aminopropylcyclohexyl POSS (and dots therein) was then washed away with chloroform to obtain the patterned structure shown in FIG. 11.

As described herein, incorporation of nanostructure arrays into devices such as flash transistors is highly desirable. Typically, non-volatile memory devices employing nanostructures such as metal nanocrystals or quantum dots for charge storage require a high, uniform density of nanostructures having a uniform size distribution. Colloidal metal nanocrystals can be synthesized with a uniform size distribution and coated on a surface with uniform density; however, at the high temperatures typically employed in transistor fabrication processes (e.g., high-temperature annealing steps following ion implantation to activate source and drain regions in substrates), metal dots tend to fuse with each other. Such fusion decreases uniformity and density of the nanostructure array and increases the size distribution of the nanostructures (see, e.g., FIG. 12 Panel A).

Among other benefits, the methods herein provide a way to protect nanostructures from such fusion: nanostructures in exposed resist can be protected from fusion during subsequent exposure to elevated temperatures. Embedding nanostructures in resist can thus not only facilitate patterning of the nanostructures, but can also help maintain their integrity.

FIG. 12 presents micrographs illustrating protection of nanostructures from fusion at high temperature by exposed silsesquioxane resist. Monolayers of ruthenium dots in aminopropylcyclohexyl POSS (see FIG. 3 Panel C, where R is a cyclohexyl group) were exposed to 950° C. for 20 seconds in a nitrogen/hydrogen atmosphere. The silsesquioxane resist was either not cured before exposure to 950° C. (Panel A), or cured with UV (ultraviolet light) in a nitrogen atmosphere for 15 minutes (Panel B) or 100 minutes (Panel C) before exposure to 950° C. Density of the dots is about 2.03×10¹²/cm² in Panel A, 2.34×10¹²/cm² in Panel B, and 2.75×10¹²/cm² in Panel C (densities for the three samples were comparable prior to heating at 950° C.). In the sample without UV curing of the silsesquioxane (Panel A), significant fusing of the quantum dots, deterioration of the film morphology, and decreased dot density are seen after 950° C. annealing. In contrast, with prior UV curing of the resist (Panels B and C), dot size, morphology, and density can be maintained. Without limitation to any particular mechanism, UV irradiation cross-links the silsesquioxane, immobilizing the dots in a cross-linked silicate matrix, preventing them from being mobile during the high temperature step and thus preventing them from fusing with each other.

Thus, when a negative resist is employed in the methods, in one aspect the methods include, after exposure of the resist in the first region and removal of unexposed resist from the second region, exposing the first layer, the exposed resist, and its embedded nanostructures to elevated temperature. Typically, the elevated temperature is at least about 300° C. (at which temperature metal dots began to fuse if not protected by exposed resist), e.g., at least about 400° C., at least about 500° C., at least about 600° C., more typically at least about 700° C., at least about 800° C., or at least about 900° C. For example, the first layer, the exposed resist, and its embedded nanostructures can be exposed to a temperature of 950° C. or more, for example, during a high-temperature annealing step. The duration of exposure to the elevated temperature can be brief, e.g., less than thirty minutes, less than ten minutes, less than one minute, less than 45 seconds, less than 30 seconds, or even 20 seconds or less (particularly for high-temperature annealing steps).

The resist is optionally cured (partially or completely) in one step before exposure to the elevated temperature. In a particularly useful aspect, however, the resist is incompletely cured by initial low dose or brief exposure to pattern the monolayer, unexposed resist and undesired nanostructures embedded therein are removed, and the incompletely cured resist is then further cured with a second exposure to protect the nanostructures during subsequent exposure to high temperature. Thus, in one class of embodiments, the resist in the first region is exposed to ionizing radiation (e.g., x-rays, UV light, or electron beam) sufficient to incompletely cure the resist in the first region, the unexposed resist and its embedded nanostructures are removed from the first layer (without removing the incompletely cured resist and its embedded nanostructures), then the incompletely cured resist in the first region is exposed to ionizing radiation sufficient to further cure the resist in the first region, before exposure to the elevated temperature. Suitable conditions for curing a variety of resists are known in the art and/or can be empirically determined. As one example, e.g., for a silsesquioxane cured by UV (e.g., UV centered at 250 nm), the resist in the first region can be exposed to about 10 mJ/cm²-1 J/cm² ultraviolet light (e.g. 1 J/cm²) to incompletely cure the resist in the first region and then to about 1 J/cm²-50 J/cm² ultraviolet light (e.g., 10 J/cm²) to further cure the resist in the first region.

By protecting the nanostructures from fusion, the techniques of the invention can maintain nanostructure density, size distribution, monolayer morphology, etc., during high temperature processing steps, as indicated above. Accordingly, in one class of embodiments, the density of nanostructures in the monolayer array after exposure to elevated temperature (e.g., 300° C. or more) is at least 75% of the density of nanostructures in the monolayer array before such exposure, more typically, at least 90% or at least 95%. Optionally, the density is essentially unchanged during the heating step. Optionally, following the elevated temperature step, the monolayer array of nanostructures has a density greater than about 1×10¹⁰ nanostructures/cm², e.g., greater than about 1×10¹¹ nanostructures/cm², greater than about 1×10¹² nanostructures/cm², at least 2×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², at least 3×10¹² nanostructures/cm², at least 4×10¹² nanostructures/cm², at least 5×10¹² nanostructures/cm², or even at least about 1×10¹³ nanostructures/cm².

As described herein, monolayers with minimal variation in nanostructure density over the monolayer can be prepared (for example, by spin coating a substrate with nanostructures dispersed in a liquid spin-on-dielectric/resist). Since the exposed resist protects the nanostructures from fusion, uniformity of the monolayer can be maintained during high temperature steps. Accordingly, in one class of embodiments, density of the nanostructures in the monolayer array is substantially uniform following the exposure to the elevated temperature. Optionally, variation in density of the nanostructures in the monolayer array is less than 10% across the monolayer, as indicated above, for example, as measured by comparing 25 nm squares within an array (or between arrays formed from a single monolayer).

In a related class of embodiments, the average diameter of the nanostructures in the monolayer array after exposure to the elevated temperature is less than 110% of the average diameter of the nanostructures in the monolayer array before such exposure, for example, less than 105% or less than 103%. Optionally, the size distribution of the nanostructures in the array is essentially unchanged during the heating step.

In another related class of embodiments, following the exposure to elevated temperature, the size distribution of the nanostructures in the monolayer array exhibits an rms deviation of less than 20%. For example, the size distribution of the nanostructures in the monolayer array can exhibit an rms deviation of less than 15%, less than 10%, or even less than 5%. The narrow size distributions achievable by colloidal synthesis of nanostructures can thus be maintained through high temperature processing step(s).

It will be evident that the tendency of nanostructures to fuse is greater at higher initial nanostructure densities, and thus protection from fusion is increasingly important with increasing nanostructure density. Thus, in embodiments in which preservation of nanostructure density, monolayer uniformity, nanostructure size, nanostructure size distribution, and/or the like is of interest, the density of nanostructures in the monolayer array before exposure to the elevated temperature is optionally at least about 1×10¹⁰ nanostructures/cm², e.g., at least about 1×10¹¹ nanostructures/cm², at least about 1×10¹² nanostructures/cm², at least 2×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², at least 3×10¹² nanostructures/cm², at least 4×10¹² nanostructures/cm², at least 5×10¹² nanostructures/cm², or even at least about 1×10¹³ nanostructures/cm².

As described above, the methods offer a convenient way to protect as well as to pattern nanostructures. The methods also offer another related advantage; in certain embodiments (e.g., with silsesquioxane resists), the unexposed resist and its embedded nanostructures is removed from the first layer by contacting the unexposed resist with at least one organic solvent. Washing the unexposed resist and embedded undesired nanostructures off with solvent is very gentle compared to etching away unwanted nanostructures, as is required with PVD dots. Avoiding the etching step avoids potential damage to the first layer on which the nanostructures are deposited, for example, a sensitive tunnel oxide layer.

As previously indicated, the methods optionally include incorporation of the array(s) into transistor(s). Thus, for example, the methods optionally include forming a source region and a drain region in the substrate in proximity to the monolayer array of nanostructures by implanting dopant ions in the substrate, wherein implantation damage to the substrate is repaired and the dopant is activated during the exposure to elevated temperature (high temperature annealing step). A gate electrode can be disposed on the exposed resist, after or, typically, before the high temperature annealing step. The exposed resist in which the nanostructure array is embedded optionally comprises a dielectric material. The exposed resist can, in some embodiments, serve as a control dielectric. In other embodiments, a dielectric layer is disposed on the exposed resist (whether the exposed resist is itself a dielectric material or not).

An exemplary embodiment is schematically illustrated in FIG. 13. In this example, first layer 1320 (e.g., a 3-4 nm thick layer of SiO₂ or another oxide, nitride, or other nonconductive material) is disposed on substrate 1321 (e.g., a Si or other semiconductor substrate). In step 1301, resist layer 1329 including monolayer 1322 of nanostructures (e.g., metal quantum dots) embedded in resist 1328 (e.g., a silsesquioxane) is disposed on the first layer. For example, the first layer can be spin coated with nanostructures dispersed in the resist. In photolithography step 1302, resist in first region 1333 is exposed and incompletely cured (e.g., by electron beam or UV), while resist in second regions 1334 is protected by mask 1335 and remains unexposed. Unexposed resist is removed in step 1303 (e.g., washed off with an organic solvent). In step 1304, the resist is further cured, for example, by exposure to electron beam or UV at higher dose. Optional additional steps can be included to burn off organic substituents (e.g., in embodiments in which a silsesquioxane with organic substituents is employed as the resist) and/or to make the resulting matrix less porous; for example, the substrate can be maintained at 300-400° C. (e.g., for 5 to 30 minutes; e.g., in an oxygen-containing environment, a nitrogen atmosphere, a nitrogen/hydrogen atmosphere such as forming gas, or water vapor) and then optionally at 950° C. (e.g., for about 20 seconds; e.g., in a nitrogen or nitrogen/hydrogen atmosphere). In step 1305, control dielectric layer 1323 (e.g., an oxide such as SiO₂ or Al₂O₃, an insulating polymer, or another nonconductive material), source electrode 1340, drain electrode 1341, and gate electrode 1342 are deposited and lithographically defined. Finally, in step 1306, source region 1330 and drain region 1331, which are separated by channel region 1337, are created in substrate 1321 by ion implantation and activation, producing transistor 1350. The cured resist protects the nanostructures during the high temperature annealing step that activates the source and drain regions. As noted above, preferred tunnel and control dielectric layers and gate electrodes are described in U.S. patent application Ser. No. 11/743,085 and U.S. Provisional Patent Application Ser. No. 60/931,488, respectively.

In any of the embodiments herein, one or more additional monolayers (or monolayer arrays) are optionally disposed on the monolayer (or array) described. Thus, the methods optionally include disposing a second monolayer of nanostructures on the resist layer or on the exposed resist. Third, fourth, etc., monolayers can also be disposed on the second, third, etc. The various layers are optionally disposed and then patterned at the same time, or the first monolayer can be patterned before the second is disposed on it and then patterned, e.g., essentially as described above. A dielectric layer is optionally disposed between adjacent nanostructure monolayers.

A related general class of embodiments provides methods for protecting nanostructures from fusion during high temperature processing. The methods include a) disposing the nanostructures and a silsesquioxane on a first layer, b) curing the silsesquioxane, to provide cured silsesquioxane in which the nanostructures are embedded, and c) heating the first layer, the cured silsesquioxane, and its embedded nanostructures. The cured silsesquioxane can form a matrix that surrounds or separates the nanostructures and protects them from fusion during the heating step, as described for the embodiments above.

The nanostructures and the silsesquioxane can be disposed on the first layer using essentially any convenient technique. For example, the first layer can be spin coated with a solution comprising the silsesquioxane and the nanostructures. The nanostructures can, but need not, form a monolayer on the first layer.

The silsesquioxane can be cured by heating it, typically, at temperatures less than about 500° C. For example, the silsesquioxane can be cured by exposure to a temperature between about 300° C. and 400° C., e.g., for five to 30 minutes. In such embodiments, steps b) and c) can be contemporaneous, or step c) can follow step b). As another example, the silsesquioxane can be cured by exposure to ionizing radiation (e.g., x-ray, UV, or electron beam), typically prior to step c). In one class of embodiments, the silsesquioxane is exposed to ionizing radiation sufficient to essentially completely cure the silsesquioxane. The silsesquioxane is optionally cured in one step. In a particularly useful aspect, however, the silsesquioxane is incompletely cured as the nanostructures are patterned and is then subsequently further cured.

Thus, in one class of embodiments, in step b) curing the silsesquioxane comprises b) i) exposing the silsesquioxane to ionizing radiation in a predetermined pattern, whereby the silsesquioxane in at least a first region is exposed and incompletely cured while the silsesquioxane in a least a second region remains unexposed and uncured, b) ii) removing the unexposed silsesquioxane and nanostructures therein from the second region without removing the incompletely cured silsesquioxane and its embedded nanostructures from the first region, and b) iii) after step ii), exposing the incompletely cured silsesquioxane in the first region to ionizing radiation to further cure the silsesquioxane, to provide the cured silsesquioxane. In one exemplary class of embodiments, in step b) i) the silsesquioxane in the first region is exposed to about 10 mJ/cm²-1 J/cm² ultraviolet light (e.g., 1 J/cm², 250 nm) to incompletely cure the silsesquioxane in the first region, and in step b) iii) the incompletely cured silsesquioxane in the first region is exposed to about 1 J/cm²-50 J/cm² ultraviolet light (e.g., 10 J/cm², 250 nm) to further cure the silsesquioxane in the first region. Unexposed silsesquioxane and nanostructures therein can be removed from the second region without removing the incompletely cured silsesquioxane and its embedded nanostructures from the first region by, e.g., contacting the unexposed silsesquioxane with at least one organic solvent.

After step b) iii) and before step c), the cured silsesquioxane is optionally exposed to a temperature between about 300° C. and 400° C. (e.g., for 5 to 30 minutes; e.g., in an oxygen-containing environment, a nitrogen atmosphere, a nitrogen/hydrogen atmosphere such as forming gas, or water vapor), and is then (or instead) optionally exposed to a temperature of about 950° C. (e.g., for about 20 seconds; e.g., in a nitrogen or nitrogen/hydrogen atmosphere). The optional additional step(s) can be included to burn off organic substituents (in embodiments in which a silsesquioxane with organic substituents is employed) and/or to make the resulting matrix less porous. Optionally, the methods result in the nanostructures embedded in a matrix consisting essentially of SiO₂ formed from the silsesquioxane.

Optionally, in step c) the first layer, the cured silsesquioxane, and its embedded nanostructures are exposed to a temperature of at least about 300° C. (typically, following step b), e.g., at least about 400° C., at least about 500° C., at least about 600° C., more typically at least about 700° C., at least about 800° C., or at least about 900° C. For example, the first layer, the cured silsesquioxane, and its embedded nanostructures can be exposed to a temperature of 950° C. or more, for example, during a high-temperature annealing step. The duration of the exposure can be brief, e.g., less than thirty minutes, less than ten minutes, less than one minute, less than 45 seconds, less than 30 seconds, or even 20 seconds or less (particularly for high-temperature annealing steps).

As noted above, the nanostructures disposed on the first layer optionally comprise a monolayer. In embodiments in which a monolayer is patterned in step b), in step b) ii) at least one nanostructure monolayer array defined by the first region remains on the first layer. The methods can be used to produce essentially any number of monolayer arrays. For example, the exposed silsesquioxane can be provided in two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, or 1×10¹² or more discrete first regions, such that two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, or 1×10¹² or more discrete nanostructure monolayer arrays remain on the first layer.

As described above, by protecting the nanostructures from fusion, the methods can maintain nanostructure density, size, size distribution, monolayer morphology, etc., during high temperature processing steps, whether or not the nanostructures are arrayed in a monolayer. For example, in one class of embodiments in which the nanostructures were disposed in a monolayer, the density of nanostructures in the monolayer array after step c) is at least 75% of the density of nanostructures in the monolayer array before step c), more typically, at least 90% or at least 95%. Optionally, the density is essentially unchanged during the heating step. As described above, protection from fusion is increasingly important with increasing nanostructure density. Thus, the density of nanostructures in the monolayer array before step c) is optionally at least about 1×10¹⁰ nanostructures/cm², e.g., at least about 1×10¹¹ nanostructures/cm², at least about 1×10¹² nanostructures/cm², at least 2×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², at least 3×10¹² nanostructures/cm², at least 4×10¹² nanostructures/cm², at least 5×10¹² nanostructures/cm², or even at least about 1×10¹³ nanostructures/cm². In one class of embodiments, following step c), the monolayer array of nanostructures has a density greater than about 1×10¹⁰ nanostructures/cm², e.g., greater than about 1×10¹¹ nanostructures/cm², greater than about 1×10¹² nanostructures/cm², at least 2×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², at least 3×10¹² nanostructures/cm², at least 4×10¹² nanostructures/cm², at least 5×10¹² nanostructures/cm², or even at least about 1×10¹³ nanostructures/cm². Optionally, density of the nanostructures in the monolayer array is substantially uniform following step c).

In one class of embodiments, the average diameter of the nanostructures embedded in the cured silsesquioxane after step c) is less than 110% of the average diameter of the nanostructures embedded in the cured silsesquioxane before step c), for example, less than 105% or less than 103%. Optionally, the size distribution of the nanostructures embedded in the cured silsesquioxane is essentially unchanged during step c). In a related class of embodiments, the size distribution of the nanostructures embedded in the cured silsesquioxane exhibits an rms deviation of less than 20%. For example, following step c), the size distribution of the nanostructures embedded in the cured silsesquioxane can exhibit an rms deviation of less than 15%, less than 10%, or even less than 5%.

In embodiments in which the nanostructures are disposed in a monolayer, the methods optionally include disposing one or more additional monolayers on the monolayer. For example, in one class of embodiments, the methods include, after step b) i) and prior to step b) iii), disposing a second monolayer of nanostructures in silsesquioxane on the incompletely cured silsesquioxane. The second monolayer can then be patterned as described for the first. As an alternative, the various layers can be disposed and then patterned simultaneously. A dielectric layer is optionally disposed between adjacent nanostructure monolayers.

Essentially all of the features noted for the methods above apply to these embodiments as well, as relevant; for example, with respect to composition of the first layer, treatment of the first layer, disposition of the first layer on a substrate, composition of the substrate, nanostructure shape and composition, size of the array(s), and the like. It is worth noting that, in embodiments in which monolayer arrays are produced, the monolayer array (or each of multiple arrays) can comprise an ordered array or, typically, a disordered array.

In embodiments in which one or more monolayer arrays are produced, the methods optionally include incorporating the array(s) into transistor(s). Thus, for example, the methods optionally include forming a source region and a drain region in the substrate in proximity to the monolayer array by, prior to step c), implanting dopant ions in the substrate, wherein implantation damage to the substrate is repaired and the dopant is activated during step c). A gate electrode can be disposed on the cured silsesquioxane, after or, typically, before the step c). A dielectric layer can be disposed on the cured silsesquioxane (i.e., on the nanostructure array) before the gate electrode is disposed.

A variety of suitable silsesquioxanes have been described herein, such as mercapto-propyl-cyclohexyl polyhedral oligomeric silsesquioxane, hydrogen silsesquioxane, methyl silsesquioxane, octavinyl dimethyl silyl silsesquioxane, octasilane silsesquioxane, octavinyl-T8 silsesquioxane, aminopropylcyclohexyl polyhedral oligomeric silsesquioxane, acrylo silsesquioxane, or methacrylo silsesquioxane, or a combination thereof. See also FIG. 3 Panels A-E. Additional silsesquioxanes are commercially available or readily produced by one of skill in the art.

In embodiments in which the nanostructures are metal nanostructures, if the nanostructures are oxidized and converted to a metal oxide during a heating step (particularly heating in an oxidizing atmosphere), they are optionally subsequently reduced by heating them in a reducing atmosphere (e.g., an atmosphere comprising hydrogen, e.g., a forming gas).

As noted, devices produced by or useful in practicing the methods of the invention are also a feature of the invention. Thus, another general class of embodiments provides a device comprising a first layer, a monolayer array of nanostructures disposed on the first layer, and resist disposed on the first layer. In one class of embodiments, the resist comprises a resist layer disposed on the monolayer array of nanostructures. See, e.g., device 460 in FIG. 4. In another class of embodiments, the resist occupies a first region of the first layer and the monolayer array of nanostructures occupies a second region of the first layer, adjacent to the first region. In yet another class of embodiments, the monolayer array of nanostructures is embedded in the resist (see, e.g., arrays 1045 in FIG. 10).

Essentially all of the features noted for the methods above apply to these embodiments as well, as relevant; for example, with respect to composition of the first layer, coating of the first layer, disposition of the first layer on a substrate, composition of the substrate, incorporation of the array(s) into transistor(s), nanostructure shape and composition, nanostructure ligands, size and density of the array(s), inclusion of a second monolayer disposed on the first, and the like. It is worth noting that the monolayer array (or each of multiple arrays) can comprise an ordered array or a disordered array.

Devices for Monolayer Formation

One aspect of the invention provides devices and methods of using the devices for forming nanostructure arrays. Thus, one general class of embodiments provides a device comprising a first layer, a second layer, a cavity between the first and second layers, one or more spacers, and at least one aperture. The one or more spacers are positioned between the first and second layers and maintain a distance between the first and second layers. The at least one aperture connects the cavity with an exterior atmosphere. The cavity is occupied by a population of nanostructures.

As will be described in greater detail below, the device can be used to form a nanostructure array. In brief, a solution of nanostructures is introduced into the cavity, and the solvent is evaporated from the cavity. As the solvent evaporates, the nanostructures assemble into an array on the first layer. The speed of evaporation can be controlled and slow, such that the nanostructures assemble into an ordered array.

Thus, in one class of embodiments, the nanostructures are dispersed in at least one solvent, while in other embodiments, the nanostructures are substantially free of solvent. The nanostructures optionally comprise an array disposed on the first layer. The array can comprise a disordered array, but in certain embodiments, the array comprises an ordered array. The array preferably comprises a monolayer, e.g., an ordered monolayer such as a hexagonal-close-packed monolayer, but optionally comprises more than a monolayer.

The first and second layers are typically substantially planar and substantially parallel to each other. Suitable materials for the first layer include, but are not limited to, those described above; for example, a dielectric material such as an oxide (e.g., silicon oxide, hafnium oxide, and alumina) or a nitride. The first layer optionally includes a coating comprising a composition that includes a nanostructure association group. Exemplary coating compositions and nanostructure association groups have been described above.

The first layer can be disposed on a substrate. Exemplary substrates have also been described above; for example, a semiconductor substrate can be used if the resulting array of nanostructures is to be incorporated into a transistor or similar device. It will be evident that multiple devices can be disposed on a single substrate and used to simultaneously produce essentially any desired number and/or size of nanostructure arrays at predetermined positions on the substrate (e.g., two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more arrays).

The second layer and/or the spacer(s) can comprise essentially any suitable material. For example, the second layer and/or the spacer(s) can comprise a metal or a dielectric material (e.g., aluminum, nickel, chromium, molybdenum, ITO, a nitride, or an oxide).

The distance between the first and second layers is greater than an average diameter of the nanostructures. The distance can be about two times the average diameter of the nanostructures or more, although to encourage formation of a monolayer of nanostructures, in certain embodiments, the distance between the first and second layers is less than about two times the average diameter of the nanostructures. For example, for quantum dots having an average diameter of about 3-5 nm, the distance would be less than about 6-10 nm.

The device can be of essentially any desired size and/or shape. In one class of embodiments, the first layer has four edges. The first and second layers are separated by two spacers, which run along two opposite edges of the first layer. Two apertures, which run along the remaining two opposite edges of the first layer, connect the cavity with the exterior atmosphere, e.g., to permit the solvent to escape as it evaporates. It will be evident that a large number of other configurations are possible. As just one additional example, the first layer can have four edges and four corners, with a spacer at each corner and an aperture along each edge, or the device can be circular, irregularly shaped, or the like.

Formation of the nanostructure array can be facilitated by application of an electric field across the cavity (see, e.g., Zhang et al., “In situ observation of colloidal monolayer nucleation driven by an alternating electric field” Nature 429:739-743 (2004)). Thus, in one class of embodiments, the first layer comprises or is disposed on a first conductive material, and the second layer comprises or is disposed on a second conductive material. Conductive materials include, but are not limited to, a metal, a semiconductor, ITO, and the like. Note that the presence of an insulating layer on either or both faces of the cavity (e.g., a dielectric first layer) does not preclude the application of such a field.

The nanostructures can comprise, e.g., short nanorods, substantially spherical nanostructures or quantum dots, and can comprise essentially any desired material. Nanostructures are described in greater detail below in the section entitled “Nanostructures”.

An example embodiment is schematically illustrated in FIG. 5, Panels A-C. In this example, device 501 includes first layer 502, second layer 503, cavity 504 between the first and second layers, and two spacers 505. The spacers are positioned between the first and second layers and maintain distance 506 between them. Two apertures 510 connect cavity 504 with external atmosphere 513. The cavity is occupied by a population of nanostructures 511, which in Panels A and B are dispersed in solvent 512, while in Panel C, they comprise array 515 disposed on the first layer.

As noted, methods using devices of the invention form another feature of the invention. Thus, one general class of embodiments provides methods for forming a nanostructure array. In the methods, a device comprising a first layer, a second layer, and a cavity between the first and second layers is provided. A solution comprising nanostructures dispersed in at least one solvent is introduced into the cavity. At least a portion of the solvent is evaporated from the cavity, whereby the nanostructures assemble into an array disposed on the first layer.

An exemplary method is schematically illustrated in FIG. 5, which depicts a cavity comprising nanostructures dispersed in a solvent in Panel A. The nanostructures draw together as the solvent evaporates (Panel B) and assemble into an array on the first layer (Panel C). The second layer is removed (Panel D); in this example, the spacers are also removed, leaving the nanostructure array disposed on the first layer.

The array is optionally incorporated into a device, e.g., a memory device; for example, the nanostructure array can comprise the gate area of a flash transistor. It will be evident that the methods can be used to form essentially any number of nanostructure arrays simultaneously, at predetermined positions (e.g., two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more).

Essentially all of the features noted for the devices above apply to the methods as well, as relevant; for example, with respect to configuration of the device; composition of the first layer and/or spacers; type of nanostructures; configuration of the resulting array; and/or the like.

The device can be fabricated, e.g., using conventional lithographic, MEMS, and/or integrated circuit techniques. In one aspect, providing the device includes disposing a third layer on the first layer, disposing the second layer on the third layer, and removing at least a portion of the third layer, whereby the cavity between the first and second layers is formed. The third layer or portion thereof can be removed, e.g., by etching away the third layer with an etchant, e.g., an anisotropic etchant. For example, the third layer can comprise polysilicon (i.e., polycrystalline silicon), amorphous silicon, molybdenum or titanium, and the etchant can comprise XeF₂.

It will be evident that the thickness of the third layer which is removed defines the height of the resulting cavity between the first and second layers. Thus, the third layer has a thickness that is greater than an average diameter of the nanostructures. The third layer can have a thickness of about two times the average diameter of the nanostructures or more, although to encourage formation of a monolayer of nanostructures, in certain embodiments, the third layer has a thickness that is less than about two times the average diameter of the nanostructures.

The first and second layers are typically separated by one or more spacers, which maintain the distance between the first and second layers when the third layer is removed. As noted, the resulting device can be of essentially any size and/or shape, so a large number of configurations for the first, second, and third layers and the spacers are possible. For example, in one class of embodiments, the first layer has four edges. The first and second layers are separated by two spacers, which run along two opposite edges of the first layer. The resulting device thus has two apertures running along the remaining two opposite ages. Alternatively, the device can have more or fewer spacers, spacers at corners instead of edges, can be circular or irregular in shape, and the like.

An exemplary method for providing a device is schematically illustrated in FIG. 6 Panel A. In this example, a relatively thick layer 610 comprising, e.g., the same material as the desired first layer (e.g., SiO₂ or another dielectric material) disposed on substrate 611 (e.g., a Si or other semiconductor substrate) is provided. In step 601, layer 610 is masked and stripes are etched into it. In step 602, a thin layer of material is disposed to form first layer 612. In step 603, third layer 613 is disposed on first layer 612 (e.g., a polysilicon third layer can be disposed by chemical vapor deposition). In step 604, second layer 614 is disposed on third layer 613 (e.g., a thin metal second layer can be evaporated onto the third layer). The thick, remaining portions of layer 610 comprise spacers 615. In step 605, the third layer is etched away to leave cavities 616 in device 620. In this example, two devices are fabricated simultaneously on the same substrate.

Another exemplary method for providing a device is schematically illustrated in FIG. 6 Panel B. In this example, thin first layer 660 is provided on substrate 661. In step 651, third layer 662 is disposed on first layer 660. In step 652, third layer 662 is masked and stripes are etched in it. In step 653, metal is deposited to form second layer 665 and spacers 666. The device is optionally masked and etched in stripes perpendicular to those previously formed, to provide free edges for an etchant to access the third layer on opposite sides. In step 654, the third layer is etched away to leave cavities 670 in device 671. Again, in this example, two devices are fabricated simultaneously on the same substrate.

The first layer optionally comprises a coating comprising a composition including a nanostructure association group. Thus, the methods optionally include coating the first layer with a composition comprising a nanostructure association group, prior to disposing the third layer on the first layer. Exemplary coating compositions and nanostructure association groups have been described above.

Nanostructures can be conveniently introduced into the cavity by, e.g., capillary action. In one class of embodiments, the solution of nanostructures is introduced into the cavity by immersing the device in an excess of the solution, permitting the solution to be drawn into the cavity by capillary action, and removing the device from the excess of the solution.

Part or substantially all the solvent is evaporated. A rate of evaporation of the solvent can be controlled, e.g., to control array formation. For example, slow evaporation of the solvent gradually increases the concentration of nanostructures, which can be conducive to formation of an ordered array of nanostructures, e.g., an ordered monolayer such as a hexagonal-close-packed monolayer.

The process of solvent evaporation can create lateral motion of the nanostructures, which can contribute to formation of an ordered array. Additional motion of the nanostructures can be encouraged, e.g., by applying an AC voltage across the cavity after introducing the solution into the cavity (e.g., prior to or simultaneous with evaporation of the solvent). See Zhang et al. (supra), which indicates that an AC voltage can generate eddy currents in the solution that give rise to lateral motion of the nanostructures, contributing to formation of an ordered array (e.g., a hexagonal-close-packed monolayer).

When evaporation and array formation have proceeded as far as desired, the second layer is removed. Optionally, any extraneous nanostructures (e.g., any nanostructures greater than a monolayer) and/or any remaining solvent can also be removed, e.g., by washing. The second layer can, for example, be etched away, or the spacers can be etched away and the second layer lifted off, e.g., by washing with a solvent, without disturbing the nanostructure array. Similarly, a layer of resist can be disposed on the spacers under the second layer, or under the spacers on the first layer, to facilitate lifting off the second layer by soaking in a suitable solvent.

Another general class of embodiments provides a device including a solid support comprising at least one vertical discontinuity on its surface. The discontinuity comprises a protrusion from the surface or an indentation in the surface. The protrusion or indentation is at a predetermined position on the solid support. The device also includes a population of nanostructures disposed on the protrusion or in the indentation.

As will be described in greater detail below, the device can be used to form a nanostructure array. In brief, a solution of nanostructures is deposited on the solid support, and the solvent is evaporated. As the solvent evaporates, the nanostructures assemble into an array on the protrusion or in the indentation. The speed of evaporation can be controlled and slow, such that the nanostructures assemble into an ordered array.

Thus, in one class of embodiments, the nanostructures are dispersed in at least one solvent, while in other embodiments, the nanostructures are substantially free of solvent. The nanostructures optionally comprise an array disposed on the protrusion or in the indentation. The array can comprise a disordered array, but in certain embodiments, the array comprises an ordered array. The array preferably comprises a monolayer, e.g., an ordered monolayer such as a hexagonal-close-packed monolayer, but optionally comprises more than a monolayer.

In a preferred class of embodiments, the solid support comprises a first layer. The solid support optionally also includes a substrate on which the first layer is disposed. In one class of embodiments, the first layer includes a coating comprising a composition comprising a nanostructure association group. Exemplary materials for the first layer and substrate, and exemplary coating compositions and nanostructure association groups, have been described above. Essentially all of the features noted in the embodiments above apply these embodiments as well, as relevant; for example, with respect to type of nanostructures (e.g., short nanorods, substantially spherical nanostructures, quantum dots, or the like).

It will be evident that a single solid support can comprise multiple devices, which can be used to simultaneously produce essentially any desired number and/or size of nanostructure arrays at predetermined positions on the solid support (e.g., on a substrate comprising the support, e.g., two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more arrays).

Exemplary embodiments are schematically illustrated in FIG. 7, Panels Letter A-C. In one example, device 701 comprises solid support 702, which includes first layer 708 and substrate 709. Surface 703 of solid support 702 includes a plurality of vertical discontinuities 704, which comprise protrusions 705 from the surface (Panels A-B). Panel B also illustrates a population of nanostructures 710, dispersed in solvent 711 or in array 713, disposed on protrusions 705. In a second example, device 751 (Panel C) comprises solid support 752, which includes first layer 758 and substrate 759. Surface 753 of solid support 752 includes a plurality of vertical discontinuities 754, which comprise indentations 755 in the surface.

The devices can be fabricated, e.g., using conventional lithographic, MEMS, and/or integrated circuit techniques, e.g., by masking and etching the first layer.

As noted, methods using devices of the invention form another feature of the invention. Thus, one general class of embodiments provides methods for forming a nanostructure array. In the methods, a solid support comprising at least one vertical discontinuity on its surface is provided. The discontinuity comprises a protrusion from the surface or an indentation in the surface, and the protrusion or indentation is at a predetermined position on the solid support. A solution comprising nanostructures dispersed in at least one solvent is deposited on the solid support. At least a portion of the solvent is evaporated, whereby the nanostructures assemble into an array disposed on the protrusion or in the indentation.

An exemplary method is schematically illustrated in FIG. 7 Panel B. In step 721, a solution of nanostructures 710 in solvent 711 is deposited on solid support 702, which includes protrusions 705 from surface 703. As the solvent evaporates, the concentration of nanostructures increases. The solvent eventually de-wets the surface in some areas, clinging to the protrusions and de-wetting in the space between the protrusions. Convection currents within the now-isolated droplets of solvent can provide lateral mobility to the nanostructures, facilitating their self-assembly. Eventually, as evaporation proceeds, solvent surface tension results in a droplet of solvent remaining on top of the protrusion (step 722). Substantially all of the solvent can be evaporated away, or evaporation can be halted once assembly of the nanostructures has reached the desired stage. Removal of any remaining solvent, and optionally of any nanostructures greater than a monolayer and/or any nanostructures left in between the protrusions, leaves array 713 of nanostructures disposed on the protrusion (step 723).

The array is optionally incorporated into a device, e.g., a memory device; for example, the nanostructure array can comprise the gate area of a flash transistor. It will be evident that the methods can be used to form essentially any number of nanostructure arrays simultaneously, at predetermined positions, e.g., two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more arrays.

Essentially all of the features noted for the devices above apply to the methods as well, as relevant; for example, with respect to configuration of the device, type of nanostructures, configuration of the resulting array, and/or the like.

In a preferred class of embodiments, the solid support comprises a first layer. The solid support optionally also includes a substrate on which the first layer is disposed. The first layer optionally comprises a coating comprising a composition including a nanostructure association group. Thus, the methods optionally include coating the first layer with a composition comprising a nanostructure association group, prior to depositing the solution on the first layer. Exemplary materials for the first layer and substrate, and exemplary coating compositions and nanostructure association groups, have been described above.

The solution containing the nanostructures can be deposited on the solid support by any of a variety of techniques, including, for example, spin-coating the solution on the solid support, dip-coating the solution on the solid support, soaking the solid support in an excess of the solution, or spray coating the solid support with the solution.

Part or substantially all the solvent is evaporated. A rate of evaporation of the solvent can be controlled, e.g., to control array formation. For example, slow evaporation of the solvent gradually increases the concentration of nanostructures, which can be conducive to formation of an ordered array of nanostructures, e.g., an ordered monolayer such as a hexagonal-close-packed monolayer.

Devices Including Nanostructure Arrays

The methods and devices described above can be used to produce nanostructure arrays at predetermined positions, and these arrays can be incorporated into devices such as memory devices, LEDs, and the like. Thus, in one aspect, the invention provides devices including nanostructure arrays, including arrays of predetermined location and/or size.

One general class of embodiments provides a device that includes a substrate and two or more nanostructure arrays disposed on the substrate. Each nanostructure array is disposed at a predetermined position on the substrate. As noted, the device is optionally produced by a method of the invention; exemplary devices are schematically illustrated in FIG. 1 (device 101) and FIG. 2 (device 201).

The substrate can comprise essentially any desired material, depending, e.g., on the desired use of the nanostructure arrays. Suitable substrates include, but are not limited to: a semiconductor; a uniform substrate, e.g., a wafer of solid material, such as silicon or other semiconductor material, glass, quartz, polymerics, etc.; a large rigid sheet of solid material, e.g., glass, quartz, plastics such as polycarbonate, polystyrene, etc.; a flexible substrate, such as a roll of plastic such as polyolefin, polyamide, and others; or a transparent substrate. Combinations of these features can be employed. The substrate optionally includes other compositional or structural elements that are part of an ultimately desired device. Particular examples of such elements include electrical circuit elements such as electrical contacts, other wires or conductive paths, including nanowires or other nanoscale conducting elements, optical and/or optoelectrical elements (e.g., lasers, LEDs, etc.), and structural elements (e.g., microcantilevers, pits, wells, posts, etc.).

The nanostructures can, but need not be, in physical contact with the substrate. Thus, in one class of embodiments, a first layer is disposed between the nanostructure arrays and the substrate. Exemplary materials for the first layer have been described above. The first layer optionally includes a coating comprising a composition including a nanostructure association group; exemplary compositions and nanostructure association groups have likewise been described above.

In one class of embodiments, the first layer comprises a dielectric material and has a thickness of between about 1 nm and about 10 nm, e.g., between 3 and 4 nm. The first layer can serve as a tunnel dielectric layer in embodiments in which the nanostructure arrays are incorporated into flash transistors or memory devices, for example. Thus, in some embodiments, for each monolayer array of nanostructures, the substrate comprises a source region, a drain region, and a channel region between the source and drain regions and underlying the monolayer array of nanostructures; a control dielectric layer is disposed on each monolayer array of nanostructures; and a gate electrode is disposed on each control dielectric layer. Preferred tunnel and control dielectric layers and gate electrodes are described in U.S. patent applicant Ser. No. 11/743,085 and U.S. Provisional Patent Applicant Ser. No. 60/931,488, respectively.

The device can include essentially any number of nanostructure arrays, for example, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more nanostructure arrays. Similarly, the arrays can be of essentially any desired size and/or shape. For example, each nanostructure array can have an area of about 10⁴ μm² or less, about 10³ μm² or less, about 10² μm² or less, about 10 μm² or less, about 1 μm² or less, about 10⁵ nm² or less, about 10⁴ nm² or less, or even about 4225 nm² or less, about 2025 nm² or less, about 1225 nm² or less, about 625 nm² or less, or about 324 nm² or less. Each nanostructure array optionally has dimensions of about 45×45 nm or less, about 35×35 nm or less, about 25×25 nm or less, or about 18×18 nm or less.

In one aspect, each nanostructure array comprises an ordered array and/or a monolayer, e.g., a hexagonal-close-packed monolayer. For many applications, however, ordered arrays are not required. For example, for arrays for use in memory devices, the nanostructures need not be ordered in the arrays as long as they achieve sufficient density in disordered arrays. Thus, in another aspect, each nanostructure array comprises a disordered array, e.g., a disordered monolayer array. The nanostructure arrays (e.g., disordered monolayer arrays) are optionally embedded in a solid form of a spin-on-dielectric or a solid form of a spin-on-glass.

In one class of embodiments, the arrays have a high density of nanostructures. For example, each nanostructure array optionally has a density greater than about 1×10¹⁰ nanostructures/cm², greater than about 1×10¹¹ nanostructures/cm², greater than about 1×10¹² nanostructures/cm², at least 2×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², at least 3×10¹² nanostructures/cm², at least 4×10¹² nanostructures/cm², at least 5×10¹² nanostructures/cm², or even greater than about 1×10¹³ nanostructures/cm².

It will be evident that essentially any of the features described herein apply in any relevant combination; for example, a device having two or more disordered monolayer arrays, each with a density of greater than about 1×10¹¹ nanostructures/cm², disposed at predetermined positions on a substrate is a feature of the invention.

In one class of embodiments, the nanostructures comprise substantially spherical nanostructures or quantum dots. The nanostructures can comprise essentially any desired material, chosen, e.g., based on the desired application. For example, the nanostructures can comprise a conductive material, a nonconductive material, a semiconductor, and/or the like. In one aspect, the nanostructures comprising the arrays have a work function of about 4.5 eV or higher. Such nanostructures are useful, for example, in fabrication of memory devices, where if the work function of the nanostructures is not sufficiently high, electrons stored in the nanostructures tend to travel back across the tunnel dielectric layer, resulting in memory loss. Thus, the nanostructures (e.g., the substantially spherical nanostructures or quantum dots) optionally comprise materials such as palladium (Pd), iridium (Ir), nickel (Ni), platinum (Pt), gold (Au), ruthenium (Ru), cobalt (Co), tungsten (W), tellurium (Te), iron platinum alloy (FePt), or the like. The nanostructures comprising the arrays are typically preformed, that is, synthesized prior to their incorporation in the array. For example, in one aspect, the nanostructures are colloidal nanostructures. In one class of embodiments, each of the nanostructures comprising the arrays comprises a coating comprising a ligand associated with a surface of the nanostructure, e.g., a silsesquioxane ligand such as those described in U.S. Provisional Patent Application Ser. No. 60/632,570 (supra) or illustrated in FIG. 3 Panels A-C. In a related class of embodiments, the nanostructures comprising the arrays are encompassed by SiO₂ or other insulating shells, produced, e.g., from a silsesquioxane coating (see U.S. Provisional Patent Application Ser. No. 60/632,570). Such ligands or shells optionally control spacing between adjacent nanostructures in the arrays. Nanostructures are described in greater detail below in the section entitled “Nanostructures”.

A related general class of embodiments also provides a device that includes a substrate and two or more nanostructure arrays disposed on the substrate. The substrate comprises a semiconductor, and each nanostructure array comprises a monolayer and is disposed at a predetermined position on the substrate. For each monolayer array, the substrate comprises an activated source region, an activated drain region, and a channel region between the source and drain regions and underlying the monolayer array of nanostructures. When dopant ions (e.g., B or As) are implanted into source and drain regions of a substrate (e.g., Si), damage to the substrate lattice typically occurs and the dopant typically assumes an interstitial position in the lattice. As described above, a high-temperature annealing step is typically used to repair such implantation damage to the substrate and to activate the source and drain regions. In “activated” source and drain regions, the dopant has taken substitution position in the substrate lattice, making the source and drain regions highly conductive (since the dopant, e.g., contributes extra electrons in the conduction band or extra holes in the valence band).

Suitable substrates include, but are not limited to, a quartz substrate or a silicon wafer or a portion thereof. As for the embodiments above, the substrate optionally includes other compositional or structural elements that are part of an ultimately desired device.

In one class of embodiments, a first layer is disposed between the monolayer arrays and the substrate. Exemplary materials for the first layer have been described above. The first layer optionally includes a coating; exemplary coatings have likewise been described above. In one class of embodiments, the first layer comprises a dielectric material and has a thickness of between about 1 nm and about 10 nm, e.g., between 3 and 4 nm. The first layer can serve as a tunnel dielectric layer in embodiments in which the nanostructure arrays are incorporated into flash transistors or memory devices, for example. Thus, in some embodiments, a control dielectric layer is disposed on each monolayer array of nanostructures, and a gate electrode is disposed on each control dielectric layer. As noted for the embodiments above, preferred tunnel and control dielectric layers and gate electrodes are described in Chen U.S. patent application Ser. No. 11/743,085 and U.S. Provisional Patent Application Ser. No. 60/931,488, respectively.

Essentially all of the features noted for the embodiments above apply to these embodiments as well, as relevant; for example, with respect to nanostructure shape and composition, inclusion of preformed nanostructures, number of arrays, size and/or dimensions of the arrays, and the like. It is worth noting that the arrays can be ordered arrays or, more typically, disordered arrays. The nanostructure arrays are optionally embedded in a solid form of a spin-on-dielectric or a solid form of a spin-on-glass, a cured (partially or essentially completely cured) resist, a cured silsesquioxane, silicon dioxide, or the like, as described above.

The device is optionally produced by a method of the invention, and thus, as described above, can include nanostructures with a narrow size distribution. Thus, in one class of embodiments, the size distribution of the nanostructures in the monolayer arrays exhibits an rms deviation of less than 20%, for example, less than 15%, less than 10%, or even less than 5%.

In one class of embodiments, the arrays have a high density of nanostructures. For example, each nanostructure array optionally has a density greater than about 1×10¹° nanostructures/cm², greater than about 1×10¹¹ nanostructures/cm², greater than about 1×10¹² nanostructures/cm², at least 2×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², at least 3×10¹² nanostructures/cm², at least 4×10¹² nanostructures/cm², at least 5×10¹² nanostructures/cm², or even greater than about 1×10¹³ nanostructures/cm². Optionally, as described above, density of the nanostructures in each monolayer array (or between arrays) is substantially uniform.

In one class of embodiments, each of the two or more monolayer arrays of nanostructures disposed on the substrate has an additional monolayer array (or two or more additional arrays) of nanostructures disposed thereon. A dielectric layer is optionally disposed between adjacent monolayers. A control dielectric layer and gate electrode can be disposed on the second (or third, fourth, etc.) monolayer.

Use of nanostructures as storage elements in memory devices facilitates creation of nodes smaller than those accessible by conventional integrated circuit fabrication techniques. Thus, another general class of embodiments provides a memory device that includes at least one transistor (e.g., a MOSFET) comprising a gate area which is occupied by a monolayer array of nanostructures and which has an area of 8100 nm² or less. The gate area optionally has an area of about 4225 nm² or less, about 2025 nm² or less, about 1225 nm² or less, about 625 nm² or less, or even about 324 nm² or less. The gate area optionally has dimensions of about 65×65 nm or less, about 45×45 nm or less, about 35×35 nm or less, about 25×25 nm or less, or about 18×18 nm or less.

The device can include essentially any number of such transistors. For example, the memory device can include two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, 1×10¹⁰ or more, 1×10¹¹ or more, or 1×10¹² or more transistors.

Essentially all of the features noted for the embodiments above apply to this embodiment as well, as relevant. For example, the nanostructures comprising the monolayer array optionally comprise substantially spherical nanostructures or quantum dots, have a work function of about 4.5 eV or higher, are preformed (e.g., colloidal), and/or are encompassed by SiO₂ or other insulating shells. Similarly, the monolayer array can comprise an ordered array (e.g., a hexagonal-close-packed monolayer) or a disordered array. The monolayer array (whether ordered or disordered) optionally has a density greater than about 1×10¹⁰ nanostructures/cm², greater than about 1×10¹¹ nanostructures/cm², greater than about 1×10¹² nanostructures/cm², at least 2×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², at least 3×10¹² nanostructures/cm², at least 4×10¹² nanostructures/cm², at least 5×10¹² nanostructures/cm², or even greater than about 1×10¹³ nanostructures/cm².

One exemplary embodiment is schematically illustrated in FIG. 4, in which memory device/transistor 450 includes monolayer array 445 of nanostructures occupying gate area 449.

As noted, the methods of the invention facilitate high temperature annealing of substrates while maintaining nanostructure size, density, etc. (for example, the narrow size distributions achievable by colloidal but not PVD dots). Thus, one general class of embodiments provides a memory device that includes at least one transistor comprising a gate area which is occupied by a monolayer array of nanostructures, an activated source region, and an activated drain region, wherein the size distribution of the nanostructures in the monolayer array exhibits an rms deviation of less than 20%. For example, the size distribution of the nanostructures in the monolayer array can exhibit an rms deviation of less than 15%, less than 10%, or even less than 5%. Optionally, density of the nanostructures in the monolayer array is substantially uniform. The at least one transistor can comprise two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, or 1×10¹² or more transistors.

Essentially all of the features noted for the embodiments above apply to these embodiments as well, as relevant; for example, with respect to nanostructure shape and composition, inclusion of preformed nanostructures, size and/or dimensions of the array, inclusion of a second (third, fourth, etc.) monolayer array on the first, control dielectric, tunnel dielectric, gate electrode, and the like. It is worth noting that the array can be ordered or, more typically, disordered. The monolayer array (whether ordered or disordered) optionally has a density greater than about 1×10¹⁰ nanostructures/cm², greater than about 1×10¹¹ nanostructures/cm², greater than about 1×10¹² nanostructures/cm², at least 2×10¹² nanostructures/cm², at least 2.5×10¹² nanostructures/cm², at least 3×10¹² nanostructures/cm², at least 4×10¹² nanostructures/cm², at least 5×10¹² nanostructures/cm², or even greater than about 1×10¹³ nanostructures/cm². The nanostructures in the array are optionally embedded in a solid form of a spin-on-dielectric or a solid form of a spin-on-glass, a cured (partially or essentially completely cured) resist, a cured silsesquioxane, silicon dioxide, or the like, as described above.

Additional details of nanostructure-based memory devices, transistors, and the like can be found, e.g., in U.S. Pat. No. 7,595,528.

Nanostructures

The individual nanostructures employed in the methods and devices include, but are not limited to, a nanocrystal, a quantum dot, a nanodot, a nanoparticle, a nanowire, a nanorod, a nanotube, a nanotetrapod, a tripod, a bipod, a branched nanocrystal, or a branched tetrapod. In one aspect, the methods and devices include spherical, nearly spherical, and/or isotropic nanocrystals such as nanodots and/or quantum dots, e.g., substantially spherical nanocrystals or quantum dots having an average diameter less than about 10 nm, and optionally less than about 8 nm, 6 nm, 5 nm, or 4 nm.

The nanostructures employed in the methods and devices of the present invention can be fabricated from essentially any convenient materials. For example, the nanocrystals can comprise inorganic materials, e.g., a metal, including, e.g., Pd, Ir, Ni, Pt, Au, Ru, Co, W, Te, Ag, Ti, Sn, Zn, Fe, FePt, or the like, or a semiconducting material selected from a variety of Group II-VI, Group III-V, or Group IV semiconductors, and including, e.g., a material comprising a first element selected from Group II of the periodic table and a second element selected from Group VI (e.g., ZnS, ZnO, ZnSe, ZnTe, CdS, CdSe, CdTe, HgS, HgSe, HgTe, MgS, MgSe, MgTe, CaS, CaSe, CaTe, SrS, SrSe, SrTe, BaS, BaSe, BaTe, and like materials); a material comprising a first element selected from Group III and a second element selected from Group V (e.g., GaN, GaP, GaAs, GaSb, InN, InP, InAs, InSb, and like materials); a material comprising a Group IV element (Ge, Si, and like materials); a material such as PbS, PbSe, PbTe, AlS, AlP, and AlSb; or an alloy or a mixture thereof. The nanostructures can include a p- or n-doped semiconductor. In other embodiments, the nanostructures can include an insulating material (e.g., a metal oxide), a polymer, an organic material (e.g., carbon), and/or the like.

In one aspect, the nanostructures are preformed, i.e., fabricated prior to their use in the methods or incorporation into the devices. For example, the nanostructures can be colloidal nanostructures. Synthesis of colloidal metal nanostructures (e.g., Pd, Pt, and Ni nanostructures) is described in U.S. Provisional Patent Application Ser. No. 60/637,409, filed Dec. 16, 2004. Synthesis of colloidal III-V semiconductor nanostructures is described in Scher et al. U.S. Pat. No. 7,557,028. Additional details of nanostructure synthesis have been described in the literature (see, e.g., the following references).

Nanostructures can be fabricated and their size can be controlled by any of a number of convenient methods that can be adapted to different materials. For example, synthesis of nanocrystals of various composition is described in, e.g., Peng et al., “Shape control of CdSe nanocrystals,” Nature 404, 59-61 (2000); Puntes et al., “Colloidal nanocrystal shape and size control: The case of cobalt,” Science 291, 2115-2117 (2001); Alivisatos et al. U.S. Pat. No. 6,306,736; Alivisatos et al. U.S. Pat. No. 6,225,198; Alivisatos et al. U.S. Pat. No. 5,505,928; Alivisatos et al. U.S. Pat. No. 5,751,018; Gallagher et al. U.S. Pat. No. 6,048,616; and Weiss et al. U.S. Pat. No. 5,990,479.

Growth of nanowires having various aspect ratios, including nanowires with controlled diameters, is described in, e.g., Gudiksen et al., “Diameter-selective synthesis of semiconductor nanowires,” J. Am. Chem. Soc. 122, 8801-8802 (2000); Cui et al., “Diameter-controlled synthesis of single-crystal silicon nanowires,” Appl. Phys. Lett. 78, 2214-2216 (2001); Gudiksen et al., “Synthetic control of the diameter and length of single crystal semiconductor nanowires,” J. Phys. Chem. B 105, 4062-4064 (2001); Morales et al., “A laser ablation method for the synthesis of crystalline semiconductor nanowires,” Science 279, 208-211 (1998); Duan et al., “General synthesis of compound semiconductor nanowires,” Adv. Mater. 12, 298-302 (2000); Cui et al., “Doping and electrical transport in silicon nanowires,” J. Phys. Chem. B 104, 5213-5216 (2000); Peng et al., “Shape control of CdSe nanocrystals,” Nature 404, 59-61 (2000); Puntes et al., “Colloidal nanocrystal shape and size control: The case of cobalt,” Science 291, 2115-2117 (2001); Alivisatos et al. U.S. Pat. No. 6,306,736; Alivisatos et al. U.S. Pat. No. 6,225,198; Lieber et al. U.S. Pat. No. 6,036,774; Lieber et al. U.S. Pat. No. 5,897,945; Urbau et al., “Synthesis of single-crystalline perovskite nanowires composed of barium titanate and strontium titanate,” J. Am. Chem. Soc., 124, 1186 (2002); and Yun et al., “Ferroelectric Properties of Individual Barium Titanate Nanowires Investigated by Scanned Probe Microscopy,” Nanoletters 2, 447 (2002).

Growth of branched nanowires (e.g., nanotetrapods, tripods, bipods, and branched tetrapods) is described in, e.g., Jun et al., “Controlled synthesis of multi-armed CdS nanorod architectures using monosurfactant system,” J. Am. Chem. Soc. 123, 5150-5151 (2001); and Manna et al., “Synthesis of Soluble and Processable Rod-, Arrow-, Teardrop-, and Tetrapod-Shaped CdSe Nanocrystals,” J. Am. Chem. Soc. 122, 12700-12706 (2000).

Synthesis of nanoparticles is described in, e.g., Clark, Jr. et al. U.S. Pat. No. 5,690,807; El-Shall et al. U.S. Pat. No. 6,136,156; Ying et al. U.S. Pat. No. 6,413,489; and Liu et al., “Sol-Gel Synthesis of Free-Standing Ferroelectric Lead Zirconate Titanate Nanoparticles,” J. Am. Chem. Soc. 123, 4344 (2001).

The nanostructures optionally comprise a core-shell architecture. Synthesis of core-shell nanostructure heterostructures, namely nanocrystal and nanowire (e.g., nanorod) core-shell heterostructures, are described in, e.g., Peng et al., “Epitaxial growth of highly luminescent CdSe/CdS core/shell nanocrystals with photostability and electronic accessibility,” J. Am. Chem. Soc. 119, 7019-7029 (1997); Dabbousi et al., “(CdSe)ZnS core-shell quantum dots: Synthesis and characterization of a size series of highly luminescent nanocrysallites,” J. Phys. Chem. B 101, 9463-9475 (1997); Manna et al., “Epitaxial growth and photochemical annealing of graded CdS/ZnS shells on colloidal CdSe nanorods,” J. Am. Chem. Soc. 124, 7136-7145 (2002); and Cao et al., “Growth and properties of semiconductor core/shell nanocrystals with InAs cores,” J. Am. Chem. Soc. 122, 9692-9702 (2000). Similar approaches can be applied to growth of other core-shell nanostructures.

Growth of nanowire heterostructures in which the different materials are distributed at different locations along the long axis of the nanowire is described in, e.g., Gudiksen et al., “Growth of nanowire superlattice structures for nanoscale photonics and electronics,” Nature 415, 617-620 (2002); Bjork et al., “One-dimensional steeplechase for electrons realized,” Nano Letters 2, 86-90 (2002); Wu et al., “Block-by-block growth of single-crystalline Si/SiGe superlattice nanowires,” Nano Letters 2, 83-86 (2002); and Empedocles U.S. Patent Publication No. 2004/0026684. Similar approaches can be applied to growth of other hetero structures.

In certain embodiments, the collection or population of nanostructures is substantially monodisperse in size and/or shape. See, e.g., Bawendi et al. U.S. Pat. No. 6,576,291.

Silsesquioxane and other ligand coatings for nanostructures, SiO₂ shells, and oxidation of metal nanostructures are described in Whiteford et al. U.S. Pat. No. 7,267,875 and Whiteford et al. U.S. Patent Publication No. 2008/0118755.

While the foregoing invention has been described in some detail for purposes of clarity and understanding, it will be clear to one skilled in the art from a reading of this disclosure that various changes in form and detail can be made without departing from the true scope of the invention. For example, all the techniques and apparatus described above can be used in various combinations. All publications, patents, patent applications, and/or other documents cited in this application are incorporated by reference in their entirety for all purposes to the same extent as if each individual publication, patent, patent application, and/or other document were individually indicated to be incorporated by reference for all purposes. 

1. A memory device comprising: at least one transistor comprising: a) a gate area occupied by a first monolayer array of nanostructures, wherein a size distribution of the nanostructures in the first monolayer array exhibits an rms deviation of less than 20%; b) an activated source region; and c) an activated drain region.
 2. The memory device of claim 1, wherein the size distribution of the nanostructures in the first monolayer array exhibits an rms deviation of less than 15%.
 3. The memory device of claim 1, wherein the size distribution of the nanostructures in the first monolayer array exhibits an rms deviation of less than 10%.
 4. The memory device of claim 1, wherein density of the nanostructures in the first monolayer array is substantially uniform.
 5. The memory device of claim 1, wherein the at least one transistor comprises two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, or 1×10¹² or more transistors.
 6. The memory device of claim 1, wherein the nanostructures comprising the first monolayer array comprise substantially spherical nanostructures or quantum dots.
 7. The memory device of claim 1, wherein the nanostructures comprising the first monolayer array have a work function of about 4.5 eV or higher.
 8. The memory device of claim 1, wherein the nanostructures comprise palladium, platinum, nickel, or ruthenium.
 9. The memory device of claim 1, wherein the nanostructures comprising the first monolayer array are preformed.
 10. The memory device of claim 1, wherein the first monolayer array has a density greater than about 1×10¹² nanostructures/cm².
 11. The memory device of claim 1, wherein the nanostructures in the first monolayer array are embedded in SiO₂.
 12. The memory device of claim 1, further comprising a second monolayer array of nanostructures disposed on the first monolayer array of nanostructures.
 13. A method of forming a memory device, the method comprising: (a) forming at least one transistor comprising, a gate area comprising a first monolayer array of nanostructures, a source region, and a drain region; and (b) activating the source region and the drain region, wherein following step (b), the nanostructures have a size distribution in the first monolayer array exhibiting an rms deviation of less than 20%.
 14. The method of claim 13, wherein the size distribution of the nanostructures in the first monolayer array exhibits an rms deviation of less than 15%.
 15. The method of claim 13, wherein the size distribution of the nanostructures in the first monolayer array exhibits an rms deviation of less than 10%.
 16. The method of claim 13, wherein density of the nanostructures in the first monolayer array is substantially uniform.
 17. The method of claim 13, wherein forming at least one transistor comprises forming two or more, 10 or more, 50 or more, 100 or more, 1000 or more, 1×10⁴ or more, 1×10⁶ or more, 1×10⁹ or more, or 1×10¹² or more transistors.
 18. The method of claim 13, wherein the nanostructures comprising the first monolayer array comprise substantially spherical nanostructures or quantum dots.
 19. The method of claim 13, wherein the nanostructures comprising the first monolayer array have a work function of about 4.5 eV or higher.
 20. The method of claim 13, wherein the nanostructures comprise palladium, platinum, nickel, or ruthenium.
 21. The method of claim 13, wherein the nanostructures comprising the first monolayer array are preformed.
 22. The method of claim 13, wherein the first monolayer array has a density greater than about 1×10¹² nanostructures/cm².
 23. The method of claim 13, wherein step (a) further comprises embedding the nanostructures in the first monolayer array in SiO₂.
 24. The method of claim 13, further comprising: (c) forming a second monolayer array of nanostructures on the first monolayer array of nanostructures. 